|
4c10182c9f
|
rtio: refactor, use rtlink
|
2015-04-14 19:44:45 +08:00 |
|
|
601f593ac4
|
targets/kc705: do not depend on particular Migen generated signal names
|
2015-04-11 21:46:57 +08:00 |
|
Florent Kermarrec
|
bdd02a064e
|
targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
|
2015-04-11 21:32:46 +08:00 |
|
Florent Kermarrec
|
24b2bd7b6f
|
soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
|
2015-04-11 21:32:11 +08:00 |
|
|
fb75bd246e
|
targets/kc705: make AMP the default
|
2015-04-11 17:16:25 +08:00 |
|
|
b492aad1c4
|
targets/kc705: enable Ethernet core
|
2015-04-10 13:15:32 +08:00 |
|
|
44304a33b2
|
soc,runtime: define RTIO FUD channel number in targets
|
2015-04-09 00:35:11 +08:00 |
|
|
7e591bb1c7
|
targets: use _Peripherals/UP/AMP class names, share QC1 IO defs
|
2015-04-07 00:07:53 +08:00 |
|
|
277e038569
|
targets/kc705: add LED on RTIO
|
2015-04-04 22:07:23 +08:00 |
|
|
5f7161a7de
|
kc705: 16 TTLs
|
2015-04-03 15:57:25 +08:00 |
|
Florent Kermarrec
|
2995f0a705
|
remove use of _r prefix on CSRs
|
2015-04-02 18:30:44 +08:00 |
|
|
88a1707ef9
|
soc: use new location of gpio module
|
2015-04-02 17:19:00 +08:00 |
|
|
5fd7f68f48
|
targets/kc705: dual-CPU design
|
2015-04-02 16:53:57 +08:00 |
|
|
28bce9ee40
|
artiqlib -> artiq.gateware
|
2015-03-08 11:00:24 +01:00 |
|
|
4e5320be28
|
Merge branch 'master' of https://github.com/m-labs/artiq
|
2015-02-28 07:34:38 -07:00 |
|
Florent Kermarrec
|
9cf8db2f14
|
adapt code to MiSoC's changes
|
2015-02-28 07:34:11 -07:00 |
|
Joe Britton
|
0127de9bb5
|
soc: add_cpu_csr_region -> add_csr_region
|
2015-02-27 15:02:28 -07:00 |
|
|
da917f768e
|
initial kc705 support
|
2015-02-26 21:50:52 -07:00 |
|