forked from M-Labs/artiq
soc,runtime: define RTIO FUD channel number in targets
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efd1c24ed7
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@ -91,8 +91,6 @@ int rtio_pileup_count(int channel)
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return r;
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}
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#define RTIO_FUD_CHANNEL 8
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void rtio_fud_sync(void)
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{
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while(rtio_get_counter() < previous_fud_end_time);
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@ -52,6 +52,7 @@ class _Peripherals(BaseSoC):
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs.append(platform.request("user_led", 2))
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self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
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rtio_outs.append(fud)
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self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
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@ -69,9 +69,10 @@ class _Peripherals(BaseSoC):
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rtio_ins = [platform.request("pmt", i) for i in range(2)]
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rtio_ins += [platform.request("xtrig", 0)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs += [fud]
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rtio_outs += [platform.request("ext_led", 0)]
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rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
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self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
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rtio_outs.append(fud)
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self.submodules.rtiocrg = _RTIOCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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@ -78,7 +78,9 @@ class UP(BaseSoC):
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
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rtio_outs = [platform.request("ttl", i) for i in range(5)]
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self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
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rtio_outs.append(fud)
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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