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7418 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 90017da484 firmware: remove obsolete watchdog code (#1458) 2020-10-15 18:38:00 +08:00
Sebastien Bourdeauducq 6af8655cc7 README: update 2020-10-15 17:14:30 +08:00
Sebastien Bourdeauducq 840364cf0c RELEASE_NOTES: fix typo 2020-10-15 16:57:53 +08:00
Sebastien Bourdeauducq 24259523bb RELEASE_NOTES: link to issue consistently 2020-10-15 16:51:02 +08:00
Sebastien Bourdeauducq ed90450d2c README: mention Sinara in ARTIQ manifesto 2020-10-15 16:48:28 +08:00
Sebastien Bourdeauducq 0a37a3dbf7 RELEASE_NOTES: fix formatting 2020-10-15 16:45:17 +08:00
Sebastien Bourdeauducq 4027735a6d RELEASE_NOTES: fix formatting 2020-10-15 16:42:43 +08:00
Sebastien Bourdeauducq 4000adfb21 RELEASE_NOTES: update ARTIQ-6 section 2020-10-15 16:42:28 +08:00
Sebastien Bourdeauducq 59703ad31d test: stop checking for artiq_netboot 2020-10-15 16:18:56 +08:00
Sebastien Bourdeauducq 7a5996ba79 artiq_netboot: moved to git.m-labs.hk/M-Labs/artiq-netboot 2020-10-15 16:14:22 +08:00
Sebastien Bourdeauducq e66d2a6408 manual: clarify and expand nix-shell file 2020-10-15 14:31:25 +08:00
Sebastien Bourdeauducq 57ee57e7ea runtime: fix metlino si5324 init (2) 2020-10-14 18:41:56 +08:00
Sebastien Bourdeauducq ac35548d0f runtime: fix metlino si5324 init 2020-10-14 12:57:25 +08:00
Sebastien Bourdeauducq 35c61ce24d si5324: unify N31 settings when used as synthesizer 
Closes #1528
 2020-10-12 14:45:52 +08:00
hartytp a058be2ede wrpll: fix test_helper_collector 2020-10-08 19:43:12 +08:00
pca006132 d0d0a02fd0 test: added lit test for new error messages 2020-10-08 19:38:26 +08:00
pca006132 e9988f9d3b compiler: error message for custom operations 
Emit error messages for custom comparison and inclusion test,
instead of compiler crashing.
 2020-10-08 19:38:26 +08:00
Sebastien Bourdeauducq db62cf2abe wrpll: convert tests to self-checking unittests 2020-10-08 18:38:01 +08:00
Sebastien Bourdeauducq 07d43b6e5f wrpll: babysit Vivado DSP retiming 
Design now passes timing.
 2020-10-08 17:51:27 +08:00
Sebastien Bourdeauducq 7dfb4af682 kasli2: work around vivado clock constraint problem 2020-10-08 16:31:39 +08:00
Sebastien Bourdeauducq 96a5df0dc6 kasli2: add false path constraint for wrpll helper clock 2020-10-08 16:19:44 +08:00
Sebastien Bourdeauducq 6248970ef8 wrpll: clean up matlab comparison test 2020-10-08 15:40:15 +08:00
hartytp cd8c2ce713 wrpll: add test to compare collector+filter against Matlab simulation 2020-10-08 15:36:56 +08:00
hartytp d780faf4ac wrpll.si549: initialize the clock divider to a sensible value 2020-10-08 15:32:27 +08:00
hartytp e6ff2ddc32 wrpll: add more diagnostics in firmware and adapt to recent gateware changes 2020-10-08 15:32:27 +08:00
hartytp 7d7be6e711 wrpll.core: move collector into helper CD so we can get tags out while the filters are reset 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 3fa5d0b963 wrpll: clean up sign extension 2020-10-08 15:32:27 +08:00
hartytp 87911810d6 wrpll.core: add CSRs to monitor the collector outputs 2020-10-08 15:32:27 +08:00
hartytp f2f942a8b4 wrpll.ddmtd: remove CSRs from DDMTD 
We will gather then from the collector output so we can get all tags on the same cycle
 2020-10-08 15:32:27 +08:00
hartytp 85bb641917 wrpll.ddmtd: fix first edge deglitcher 
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
 2020-10-08 15:32:27 +08:00
hartytp f3cd0fc675 wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit. 
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
 2020-10-08 15:32:27 +08:00
hartytp e5e648bde1 wrpll: add bit shift for collector helper output 2020-10-08 15:32:27 +08:00
hartytp c9ae406ac6 wrpll: change the DDMTD helper frequency to match CERN, improve docs 2020-10-08 15:32:27 +08:00
hartytp f6f6045f1a wrpll.thls: fix make 2020-10-08 15:32:27 +08:00
hartytp b44b870452 wrpll.filters: update to match Weida's MatLab simulations 2020-10-08 15:32:27 +08:00
hartytp e9ab434fa7 wrpll.core: update for modified collector 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 17c952b8fb wrpll: style 2020-10-08 15:32:27 +08:00
hartytp ebb7ccbfd1 wrpll: document DDMTD collector and fix unwrapping 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 7c2519c912 manual: nixpkgs 20.09 2020-10-08 09:18:46 +08:00
Sebastien Bourdeauducq 1bfe977203 manual: sphinx mock module whack-a-mole 2020-10-07 19:25:26 +08:00
Sebastien Bourdeauducq 66401aee9c dashboard: cleanup import 2020-10-07 19:24:54 +08:00
Sebastien Bourdeauducq 6baf3b2198 RELEASE_NOTES: fix indentation 2020-10-07 19:24:34 +08:00
pca006132 fe6115bcbb compiler: fix incorrect with behavior 2020-10-07 18:59:35 +08:00
pca006132 02f46e8b79 Fixes none to bool coercion 
Fixes #1413 and #1414.
 2020-10-07 15:34:24 +08:00
pca006132 88d346fa26 fixes with statement with multiple items 
Closes #1478
 2020-10-07 15:33:34 +08:00
Sebastien Bourdeauducq 9214e0f3e2 firmware: fix Si5324 CKIN selection on Kasli 2.0 
https://github.com/sinara-hw/Kasli/issues/82#issuecomment-702129805
 2020-10-02 20:35:32 +08:00
Robert Jördens a65239957f ad53xx: distinguish errors 2020-09-24 10:52:03 +02:00
Robert Jördens c55f2222dc fastino: documentation and eem pass-through 
* Repeat information about matching log2_width a few times
  in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
 2020-09-22 17:58:53 +02:00
Sebastien Bourdeauducq 29c940f4e3 kasli2: forward sma_clkin to si5324 2020-09-17 16:53:43 +08:00
Sebastien Bourdeauducq bff611a888 test: relax test_dma_playback_time on Zynq 2020-09-11 11:21:45 +08:00