forked from M-Labs/artiq
EFC: Add SPI Gateware for Shuttler DAC
- Verified by a functional test reading back the rev register
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@ -5,7 +5,7 @@ import argparse
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import gpio
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from misoc.cores import gpio, spi2
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from misoc.targets.efc import BaseSoC
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from misoc.integration.builder import builder_args, builder_argdict
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@ -102,6 +102,24 @@ class Satellite(BaseSoC, AMPSoC):
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self.config["DRTIO_ROLE"] = "satellite"
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self.config["RTIO_FREQUENCY"] = "125.0"
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shuttler_io = [
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('dac_spi', 0,
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Subsignal('clk', Pins('fmc0:HB16_N')),
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Subsignal('mosi', Pins('fmc0:HB06_CC_N')),
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Subsignal('cs_n', Pins('fmc0:LA31_N fmc0:LA31_P fmc0:HB19_P fmc0:LA30_P')),
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IOStandard("LVCMOS18")),
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('dac_rst', 0, Pins('fmc0:HB16_P'), IOStandard("LVCMOS18")),
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]
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platform.add_extension(shuttler_io)
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self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(self.platform.request("dac_spi", 0)))
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self.csr_devices.append("converter_spi")
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self.config["HAS_CONVERTER_SPI"] = None
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dac_rst = self.platform.request('dac_rst')
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self.comb += dac_rst.eq(0)
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self.rtio_channels = []
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self.config["HAS_RTIO_LOG"] = None
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