forked from M-Labs/artiq
rtio core: fix minimum_coarse_timestamp
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@ -66,7 +66,7 @@ class Core(Module, AutoCSR):
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interface=self.cri)
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self.submodules += outputs
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self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
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self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
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self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 12)
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inputs = InputCollector(tsc, channels,
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quash_channels=quash_channels,
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