forked from M-Labs/artiq
echo test: add two more yields
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cd860beda2
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@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase):
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yield
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yield dut.master.rt_packet.echo_stb.eq(0)
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for i in range(15):
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for i in range(17):
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yield
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self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1)
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