17 Commits

Author	SHA1	Message	Date
Robert Jördens	9e726d7dd1	ppro: ignore all async paths	2015-04-14 18:18:48 -06:00
Sebastien Bourdeauducq	4c10182c9f	rtio: refactor, use rtlink	2015-04-14 19:44:45 +08:00
Sebastien Bourdeauducq	a50f2c20ff	targets/ppro: fix mem_map update	2015-04-11 21:59:29 +08:00
Florent Kermarrec	24b2bd7b6f	soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds	2015-04-11 21:32:11 +08:00
Sebastien Bourdeauducq	44304a33b2	soc,runtime: define RTIO FUD channel number in targets	2015-04-09 00:35:11 +08:00
Sebastien Bourdeauducq	7e591bb1c7	targets: use _Peripherals/UP/AMP class names, share QC1 IO defs	2015-04-07 00:07:53 +08:00
Florent Kermarrec	2995f0a705	remove use of _r prefix on CSRs	2015-04-02 18:30:44 +08:00
Sebastien Bourdeauducq	88a1707ef9	soc: use new location of gpio module	2015-04-02 17:19:00 +08:00
Yann Sionneau	e9092edb98	Remove one RTIO out channel to free up some space for travis builds to succeed	2015-03-30 19:51:52 +08:00
Florent Kermarrec	494c670cd2	targets/artiq_ppro: use new sdram_controller_settings parameter	2015-03-21 23:19:16 +01:00
Sebastien Bourdeauducq	3122623c6f	rtio: make 63-bit timestamp counter the default [soc]	2015-03-12 13:13:35 +01:00
Sebastien Bourdeauducq	28bce9ee40	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
Sebastien Bourdeauducq	4e5320be28	Merge branch 'master' of https://github.com/m-labs/artiq	2015-02-28 07:34:38 -07:00
Florent Kermarrec	9cf8db2f14	adapt code to MiSoC's changes	2015-02-28 07:34:11 -07:00
Sébastien Bourdeauducq	7028d85255	targets/ppro: disable L2	2015-02-27 18:02:21 -07:00
Joe Britton	0127de9bb5	soc: add_cpu_csr_region -> add_csr_region	2015-02-27 15:02:28 -07:00
Sebastien Bourdeauducq	da917f768e	initial kc705 support	2015-02-26 21:50:52 -07:00