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66fff6618c
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cargo: update
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2019-04-12 10:55:38 +00:00 |
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5369b928c1
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add get_x_offset
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2019-03-31 11:33:18 +00:00 |
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d7e47b7ebf
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manifest: update
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2019-03-31 11:33:03 +00:00 |
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6577d1ce01
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cargo: tweak
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2019-03-29 19:34:31 +01:00 |
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293520e26e
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iir: tweak, add offset
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2019-03-29 18:33:32 +00:00 |
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9fc6868fdf
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travis: install target
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2019-03-29 09:12:07 +00:00 |
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24c5163265
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add travis
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2019-03-29 08:52:38 +00:00 |
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dc9af3fd8e
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cargo: update
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2019-03-29 08:51:36 +00:00 |
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3b895ead4b
|
set afe1 gain
|
2019-03-29 08:37:40 +00:00 |
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74f10a7ac4
|
cleanup iir
|
2019-03-28 15:10:04 +00:00 |
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dc2e0f8b07
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dual channel
|
2019-03-28 12:13:47 +00:00 |
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7f378a3f3d
|
clean dcache
|
2019-03-28 10:47:15 +00:00 |
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9350f17ca3
|
calculate pi coefficients
|
2019-03-28 10:09:50 +00:00 |
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ed663b536e
|
add prelim iir
|
2019-03-27 21:45:43 +00:00 |
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eff2dc6c4e
|
led off
|
2019-03-27 18:24:58 +00:00 |
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31264452a6
|
irq bypass for dma
|
2019-03-27 18:19:32 +00:00 |
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|
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2eeb00bb58
|
use tim2,dma1 to trigger cr1
|
2019-03-27 13:50:25 +00:00 |
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f9e52928fd
|
use irq
|
2019-03-25 09:08:27 +00:00 |
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32ba1a74b9
|
limit backtrace
|
2019-03-20 19:28:33 +00:00 |
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|
|
aa3feeb14e
|
back to tsize=1 adc
|
2019-03-20 19:28:23 +00:00 |
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|
|
a2265ab2d1
|
experiment with duplex adc xfers
problematic because:
* in tsize=1 there needs to be a cstart
* in tsize=0 there is no mssi
|
2019-03-20 19:08:31 +00:00 |
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|
984cef6a4c
|
readme, license
|
2019-03-20 18:33:35 +00:00 |
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208980d94d
|
refactor into functions
|
2019-03-20 18:06:13 +00:00 |
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|
52a3f8c4b7
|
rxdr: 16 bit
|
2019-03-20 13:48:28 +00:00 |
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|
|
263784ff13
|
no midi
|
2019-03-20 13:31:48 +00:00 |
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|
|
d3d2d4e4f8
|
enable i/o compensation cell
|
2019-03-20 10:29:13 +00:00 |
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|
|
cbd9bcd302
|
dac: use inifinite xfers
|
2019-03-20 09:51:06 +00:00 |
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|
4f628c6a41
|
cargo: gdb-multicarch
|
2019-03-20 09:48:44 +00:00 |
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|
|
772b1b4101
|
dac tx: different work around
|
2019-03-19 22:02:16 +00:00 |
|
|
|
4ee7ccb762
|
fix afe gain
|
2019-03-19 21:52:55 +00:00 |
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|
|
bbe79e3484
|
speed up pclk again
|
2019-03-19 21:52:48 +00:00 |
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|
|
8fbb1c751b
|
work around erratum 2.10.2
|
2019-03-19 15:39:01 +00:00 |
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|
|
4b49f29b17
|
dac
|
2019-03-19 15:27:22 +00:00 |
|
|
|
b9f27791ab
|
adc
|
2019-03-18 19:10:36 +00:00 |
|
|
|
a20e0fa3e5
|
speed up
|
2019-03-18 16:57:00 +00:00 |
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|
|
44c36b203d
|
working
|
2019-03-18 13:10:00 +00:00 |
|
|
|
155aa5c032
|
start
|
2019-03-18 12:56:26 +01:00 |
|
|
|
e26b92e15f
|
Update README.md
|
2019-03-10 13:08:32 +01:00 |
|
|
|
1479931451
|
Initial commit
|
2019-03-10 13:02:03 +01:00 |
|
