Commit Graph

30 Commits

Author SHA1 Message Date
74f10a7ac4 cleanup iir 2019-03-28 15:10:04 +00:00
dc2e0f8b07 dual channel 2019-03-28 12:13:47 +00:00
7f378a3f3d clean dcache 2019-03-28 10:47:15 +00:00
9350f17ca3 calculate pi coefficients 2019-03-28 10:09:50 +00:00
ed663b536e add prelim iir 2019-03-27 21:45:43 +00:00
eff2dc6c4e led off 2019-03-27 18:24:58 +00:00
31264452a6 irq bypass for dma 2019-03-27 18:19:32 +00:00
2eeb00bb58 use tim2,dma1 to trigger cr1 2019-03-27 13:50:25 +00:00
f9e52928fd use irq 2019-03-25 09:08:27 +00:00
32ba1a74b9 limit backtrace 2019-03-20 19:28:33 +00:00
aa3feeb14e back to tsize=1 adc 2019-03-20 19:28:23 +00:00
a2265ab2d1 experiment with duplex adc xfers
problematic because:

* in tsize=1 there needs to be a cstart
* in tsize=0 there is no mssi
2019-03-20 19:08:31 +00:00
984cef6a4c readme, license 2019-03-20 18:33:35 +00:00
208980d94d refactor into functions 2019-03-20 18:06:13 +00:00
52a3f8c4b7 rxdr: 16 bit 2019-03-20 13:48:28 +00:00
263784ff13 no midi 2019-03-20 13:31:48 +00:00
d3d2d4e4f8 enable i/o compensation cell 2019-03-20 10:29:13 +00:00
cbd9bcd302 dac: use inifinite xfers 2019-03-20 09:51:06 +00:00
4f628c6a41 cargo: gdb-multicarch 2019-03-20 09:48:44 +00:00
772b1b4101 dac tx: different work around 2019-03-19 22:02:16 +00:00
4ee7ccb762 fix afe gain 2019-03-19 21:52:55 +00:00
bbe79e3484 speed up pclk again 2019-03-19 21:52:48 +00:00
8fbb1c751b work around erratum 2.10.2 2019-03-19 15:39:01 +00:00
4b49f29b17 dac 2019-03-19 15:27:22 +00:00
b9f27791ab adc 2019-03-18 19:10:36 +00:00
a20e0fa3e5 speed up 2019-03-18 16:57:00 +00:00
44c36b203d working 2019-03-18 13:10:00 +00:00
155aa5c032 start 2019-03-18 12:56:26 +01:00
e26b92e15f
Update README.md 2019-03-10 13:08:32 +01:00
1479931451
Initial commit 2019-03-10 13:02:03 +01:00