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d837f6f8f6
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Add SLLIW instruction
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2020-08-27 13:39:11 +08:00 |
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2790cb1f4c
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Add RV64I I-Type Instruction (Shift Variation)
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2020-08-27 13:28:29 +08:00 |
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a15e57e12e
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Update README.md
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2020-08-27 13:12:23 +08:00 |
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3a332c5c1d
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Add ADDIW instruction
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2020-08-27 13:11:23 +08:00 |
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dae95900b6
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Update README.md
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2020-08-27 12:54:28 +08:00 |
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0954ee7fa9
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Add SD instruction
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2020-08-27 12:53:07 +08:00 |
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472e0a70f8
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Update README.md
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2020-08-27 12:30:57 +08:00 |
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94da2671dc
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Add LD instruction
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2020-08-27 12:28:19 +08:00 |
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bd76a47a52
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Add LWU instruction
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2020-08-27 12:25:19 +08:00 |
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92e34efe0d
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Add RV64I I-Type Instruction (Load Variation)
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2020-08-27 12:20:17 +08:00 |
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0af1f20423
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Add RV64I I-Type Instruction
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2020-08-27 11:46:04 +08:00 |
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1ea25a4886
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Add RV32M Standard Extension
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2020-08-27 10:32:49 +08:00 |
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3f3ec597a1
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Update README.md
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2020-08-26 17:21:27 +08:00 |
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46e6ca3f70
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Add REMU instruction
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2020-08-26 17:15:27 +08:00 |
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fb91df7bb8
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Add REM instruction
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2020-08-26 17:11:03 +08:00 |
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33ace9147a
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Add DIVU instruction
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2020-08-26 17:03:49 +08:00 |
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0708f6b962
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Add DIV instruction
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2020-08-26 16:58:50 +08:00 |
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b74a0cf699
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Add MULHU instruction
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2020-08-26 16:43:21 +08:00 |
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a58842ea94
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Add MULHSU instruction
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2020-08-26 16:39:17 +08:00 |
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15580a74c6
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Add MULH instruction
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2020-08-26 16:30:54 +08:00 |
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585965ee0a
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Add MUL instruction
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2020-08-26 15:57:32 +08:00 |
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dd17606902
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Add RV32M R-Type Instruction
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2020-08-26 15:48:55 +08:00 |
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d7d4f8b0ad
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Reduce code duplication in Minerva verification script
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2020-08-21 11:43:20 +08:00 |
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de3ff25da1
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Refactor insns directory
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2020-08-21 10:33:02 +08:00 |
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3e527b3727
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Refactor instructions to use NamedTuple
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2020-08-20 17:28:09 +08:00 |
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73707afe78
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Modularize codebase
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2020-08-17 11:50:53 +08:00 |
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