 Donald Sebastian Leung
|
472e0a70f8
|
Update README.md
|
2020-08-27 12:30:57 +08:00 |
|
Donald Sebastian Leung
|
94da2671dc
|
Add LD instruction
|
2020-08-27 12:28:19 +08:00 |
|
Donald Sebastian Leung
|
bd76a47a52
|
Add LWU instruction
|
2020-08-27 12:25:19 +08:00 |
|
Donald Sebastian Leung
|
92e34efe0d
|
Add RV64I I-Type Instruction (Load Variation)
|
2020-08-27 12:20:17 +08:00 |
|
Donald Sebastian Leung
|
0af1f20423
|
Add RV64I I-Type Instruction
|
2020-08-27 11:46:04 +08:00 |
|
Donald Sebastian Leung
|
fe835e272d
|
Replace RV32I with RV32M for Minerva verification tasks
|
2020-08-27 10:48:35 +08:00 |
|
Donald Sebastian Leung
|
1ea25a4886
|
Add RV32M Standard Extension
|
2020-08-27 10:32:49 +08:00 |
|
Donald Sebastian Leung
|
3f3ec597a1
|
Update README.md
|
2020-08-26 17:21:27 +08:00 |
|
Donald Sebastian Leung
|
46e6ca3f70
|
Add REMU instruction
|
2020-08-26 17:15:27 +08:00 |
|
Donald Sebastian Leung
|
fb91df7bb8
|
Add REM instruction
|
2020-08-26 17:11:03 +08:00 |
|
Donald Sebastian Leung
|
33ace9147a
|
Add DIVU instruction
|
2020-08-26 17:03:49 +08:00 |
|
Donald Sebastian Leung
|
0708f6b962
|
Add DIV instruction
|
2020-08-26 16:58:50 +08:00 |
|
Donald Sebastian Leung
|
b74a0cf699
|
Add MULHU instruction
|
2020-08-26 16:43:21 +08:00 |
|
Donald Sebastian Leung
|
a58842ea94
|
Add MULHSU instruction
|
2020-08-26 16:39:17 +08:00 |
|
Donald Sebastian Leung
|
15580a74c6
|
Add MULH instruction
|
2020-08-26 16:30:54 +08:00 |
|
Donald Sebastian Leung
|
585965ee0a
|
Add MUL instruction
|
2020-08-26 15:57:32 +08:00 |
|
Donald Sebastian Leung
|
dd17606902
|
Add RV32M R-Type Instruction
|
2020-08-26 15:48:55 +08:00 |
|
Donald Sebastian Leung
|
ca9e9c9ca6
|
Add prototype for instruction/data bus implementation
|
2020-08-25 12:41:30 +08:00 |
|
Donald Sebastian Leung
|
ac7991ae86
|
Merge instruction and data bus abstractions
|
2020-08-25 10:12:02 +08:00 |
|
Donald Sebastian Leung
|
ca135d024f
|
Wire instruction and data buses (WIP) to Minerva core
|
2020-08-24 14:46:52 +08:00 |
|
Donald Sebastian Leung
|
2a4f6dd07e
|
Wire interrupt signals to Minerva for verification
|
2020-08-24 13:28:33 +08:00 |
|
Donald Sebastian Leung
|
ee80bff3db
|
Merge riscv_formal_parameters.py into verify.py
|
2020-08-24 10:20:30 +08:00 |
|
Donald Sebastian Leung
|
dad6022572
|
Replace individual instruction checks with ISA check
|
2020-08-21 15:14:42 +08:00 |
|
Donald Sebastian Leung
|
908ecf9e7e
|
Add uniqueness check
|
2020-08-21 13:25:52 +08:00 |
|
Donald Sebastian Leung
|
a7b6b7a169
|
Add liveness check
|
2020-08-21 12:54:53 +08:00 |
|
Donald Sebastian Leung
|
d7d4f8b0ad
|
Reduce code duplication in Minerva verification script
|
2020-08-21 11:43:20 +08:00 |
|
Donald Sebastian Leung
|
de3ff25da1
|
Refactor insns directory
|
2020-08-21 10:33:02 +08:00 |
|
Donald Sebastian Leung
|
3e527b3727
|
Refactor instructions to use NamedTuple
|
2020-08-20 17:28:09 +08:00 |
|
Donald Sebastian Leung
|
1a38b37473
|
Remove copy of Minerva
|
2020-08-20 15:32:10 +08:00 |
|
Donald Sebastian Leung
|
a6b4891a38
|
Add causal checks
|
2020-08-20 12:00:31 +08:00 |
|
Donald Sebastian Leung
|
2a9ddf0868
|
Add register checks
|
2020-08-20 11:10:33 +08:00 |
|
Donald Sebastian Leung
|
2383706012
|
Add PC backward checks
|
2020-08-19 17:22:03 +08:00 |
|
Donald Sebastian Leung
|
2bfd909b49
|
Add PC forward checks
|
2020-08-19 17:00:11 +08:00 |
|
Donald Sebastian Leung
|
c073411bd2
|
Add tests for all RV32I instructions
|
2020-08-19 14:56:26 +08:00 |
|
Donald Sebastian Leung
|
0e0d4b6e42
|
Add (currently failing) test case for LUI instruction
|
2020-08-18 14:10:47 +08:00 |
|
Donald Sebastian Leung
|
3faa8ed1b8
|
Add build instructions for Minerva
|
2020-08-17 16:46:15 +08:00 |
|
Donald Sebastian Leung
|
7005d22e4e
|
Add instruction check
|
2020-08-17 16:03:20 +08:00 |
|
Donald Sebastian Leung
|
73707afe78
|
Modularize codebase
|
2020-08-17 11:50:53 +08:00 |