|
036f842faa
|
Add RV32I I-Type Instruction (Arithmetic Variation)
|
2020-08-10 17:12:09 +08:00 |
|
|
d60c712704
|
Update README.md
|
2020-08-10 16:47:09 +08:00 |
|
|
42b8e5c245
|
Add LHU instruction
|
2020-08-10 16:44:08 +08:00 |
|
|
462e526e71
|
Add LBU instruction
|
2020-08-10 16:40:45 +08:00 |
|
|
7b440f0fa9
|
Add LW instruction
|
2020-08-10 16:35:37 +08:00 |
|
|
c88cf830fc
|
Add LH instruction
|
2020-08-10 16:29:42 +08:00 |
|
|
167d654be8
|
Add LB instruction
|
2020-08-10 16:26:29 +08:00 |
|
|
bfd8f670c2
|
Add RV32I I-Type Instruction (Load Variation)
|
2020-08-10 16:16:30 +08:00 |
|
|
10296cbf3b
|
Update README
|
2020-08-10 14:14:40 +08:00 |
|
|
1cae183569
|
Add JALR instruction
|
2020-08-10 14:13:25 +08:00 |
|
|
e97a86bfbe
|
Add (generic) RV32I I-Type Instruction
|
2020-08-10 13:32:04 +08:00 |
|
|
ff977c0e50
|
Update README.md
|
2020-08-10 12:59:00 +08:00 |
|
|
475c1d9fc2
|
Add SRAI instruction
|
2020-08-10 12:56:19 +08:00 |
|
|
20a500157b
|
Add attribution to SO in InsnSra.py
|
2020-08-10 12:46:09 +08:00 |
|
|
9740470c47
|
Add SRLI instruction
|
2020-08-10 12:35:49 +08:00 |
|
|
031f335325
|
Fix SLLI instruction
|
2020-08-10 12:31:20 +08:00 |
|
|
1fb51e614d
|
Add SLLI instruction
|
2020-08-10 12:29:52 +08:00 |
|
|
94faa3ba68
|
Remove redundancy in super() calls
|
2020-08-10 11:15:05 +08:00 |
|
|
9e64c7ee17
|
Add RV32I I-Type Instruction (Shift Variation)
|
2020-08-07 16:39:14 +08:00 |
|
|
1c0541cd12
|
Document RV32I R-Type Instructions
|
2020-08-07 16:06:15 +08:00 |
|
|
9bfd155b44
|
Add AND instruction
|
2020-08-07 15:57:19 +08:00 |
|
|
07e4c04b26
|
Add OR instruction
|
2020-08-07 15:54:18 +08:00 |
|
|
d06daac123
|
Add SRA instruction
|
2020-08-07 15:51:21 +08:00 |
|
|
4f7cf5a370
|
Add SRL instruction
|
2020-08-07 15:39:46 +08:00 |
|
|
d106ceede7
|
Add XOR instruction
|
2020-08-07 15:35:40 +08:00 |
|
|
cab30848e9
|
Add SLTU instruction
|
2020-08-07 15:33:18 +08:00 |
|
|
d33dc1b137
|
Add SLT instruction
|
2020-08-07 15:29:54 +08:00 |
|
|
44bdff60c8
|
Add SLL instruction
|
2020-08-07 15:25:05 +08:00 |
|
|
060dd98919
|
Add SUB instruction
|
2020-08-07 14:00:12 +08:00 |
|
|
ccc1bd098b
|
Add ADD instruction
|
2020-08-07 13:54:00 +08:00 |
|
|
4f7b11d009
|
Add RV32I R-Type Instruction
|
2020-08-07 13:45:35 +08:00 |
|
|
2e2300e5c8
|
Update insns/README.md
|
2020-08-07 12:54:31 +08:00 |
|
|
a8cf15e123
|
Add generic instruction class
|
2020-08-07 12:28:52 +08:00 |
|
|
56048099b3
|
Correct typo in insns/README.md
|
2020-08-06 16:44:54 +08:00 |
|
|
9a3cb8e88a
|
Fix table formatting in insns/README.md
|
2020-08-06 14:45:51 +08:00 |
|
|
7c420cce7a
|
Categorize all (to be) supported instructions
|
2020-08-06 14:13:00 +08:00 |
|
|
3eaed129c2
|
Begin re-organization of project structure
|
2020-08-06 12:36:01 +08:00 |
|
|
7c60451bfa
|
Add README for instructions
|
2020-08-05 12:54:46 +08:00 |
|
|
c4e30e9c55
|
Add REMU instruction
|
2020-08-04 17:17:37 +08:00 |
|
|
af8704cea0
|
Add REM instruction
|
2020-08-04 17:14:46 +08:00 |
|
|
78fb149761
|
Add DIVU instruction
|
2020-08-04 17:12:13 +08:00 |
|
|
2a809073a5
|
Add DIV instruction
|
2020-08-04 17:09:21 +08:00 |
|
|
7b39ce135f
|
Add MULHU instruction
|
2020-08-04 17:06:49 +08:00 |
|
|
ee38e3a61d
|
Add MULHSU instruction
|
2020-08-04 17:04:04 +08:00 |
|
|
a26813835f
|
Add MULH instruction
|
2020-08-04 17:00:43 +08:00 |
|
|
e1bbf567c2
|
Add MUL instruction
|
2020-08-04 16:57:43 +08:00 |
|
|
aa47b866a1
|
Add AND instruction
|
2020-08-04 12:54:46 +08:00 |
|
|
9429403616
|
Add OR instruction
|
2020-08-04 12:51:48 +08:00 |
|
|
a3a9592c19
|
Add SRA instruction
|
2020-08-04 12:47:35 +08:00 |
|
|
907f7240bf
|
Add SRL instruction
|
2020-08-04 12:42:39 +08:00 |
|