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riscv-formal-nmigen
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Add SLT instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-07 15:29:54 +08:00
parent 44bdff60c8
commit d33dc1b137
1 changed files with 11 additions and 0 deletions
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insns/InsnSlt.py Normal file
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from InsnRV32IRType import *
class InsnSlt(InsnRV32IRType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011)
def elaborate(self, platform):
m = super(InsnSlt, self).elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), 0))
return m