Document RV32I R-Type Instructions

insns/InsnAdd.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+ADD instruction
+"""
+
 class InsnAdd(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011)

insns/InsnAnd.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+AND instruction
+"""
+
 class InsnAnd(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011)

insns/InsnOr.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+OR instruction
+"""
+
 class InsnOr(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011)

insns/InsnSll.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SLL instruction
+"""
+
 class InsnSll(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011)

insns/InsnSlt.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SLT instruction
+"""
+
 class InsnSlt(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011)

insns/InsnSltu.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SLTU instruction
+"""
+
 class InsnSltu(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011)

insns/InsnSra.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SRA instruction
+"""
+
 class InsnSra(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011)

insns/InsnSrl.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SRL instruction
+"""
+
 class InsnSrl(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011)

insns/InsnSub.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+SUB instruction
+"""
+
 class InsnSub(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011)

insns/InsnXor.py

@@ -1,5 +1,9 @@
 from InsnRV32IRType import *
 
+"""
+XOR instruction
+"""
+
 class InsnXor(InsnRV32IRType):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011)

insns/README.md

@@ -35,6 +35,17 @@
 _Note: This section is under development and will be updated as more classes are implemented._
 
 - `Insn`: General RISC-V instruction
+  - `InsnRV32IRType`: RV32I R-Type Instruction
+    - `InsnAdd`: ADD instruction
+    - `InsnSub`: SUB instruction
+    - `InsnSll`: SLL instruction
+    - `InsnSlt`: SLT instruction
+    - `InsnSltu`: SLTU instruction
+    - `InsnXor`: XOR instruction
+    - `InsnSrl`: SRL instruction
+    - `InsnSra`: SRA instruction
+    - `InsnOr`: OR instruction
+    - `InsnAnd`: AND instruction
 
 ## Parameters