M-Labs/riscv-formal-nmigen
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Add LBU instruction

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This commit is contained in:
Donald Sebastian Leung 2020-08-10 16:40:45 +08:00
parent 7b440f0fa9
commit 462e526e71
1 changed files with 9 additions and 0 deletions
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insns/InsnLbu.py Normal file
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from InsnRV32IITypeLoad import *
"""
LBU instruction
"""
class InsnLbu(InsnRV32IITypeLoad):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False)