M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add AND instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-07 15:57:19 +08:00
parent 07e4c04b26
commit 9bfd155b44
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
insns/InsnAnd.py Normal file
View File

@ -0,0 +1,11 @@
from InsnRV32IRType import *
class InsnAnd(InsnRV32IRType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011)
def elaborate(self, platform):
m = super(InsnAnd, self).elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.rvfi_rs2_rdata, 0))
return m