riscv-formal-nmigen/insns

RISC-V Supported Instructions

Instructions

Instruction type	Instructions
R-type	ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR
I-type	ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI
I-type (shift variation)	SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW
S-type	SB, SD, SH, SW
SB-type	BEQ, BGE, BGEU, BLT, BLTU, BNE
U-type	AUIPC, LUI
UJ-type	JAL
CI-type	C_ADD, C_ADDI, C_ADDIW, C_JALR, C_JR, C_LI, C_MV
CI-type (SP variation)	C_ADDI16SP
CI-type (ANDI variation)	C_ANDI
CI-type (LSP variation, 32 bit version)	C_LWSP
CI-type (LSP variation, 64 bit version)	C_LDSP
CI-type (LUI variation)	C_LUI
CI-type (SLI variation)	C_SLLI
CI-type (SRI variation)	C_SRAI, C_SRLI
CIW-type	C_ADDI4SPN
CS-type (ALU version)	C_ADDW, C_AND, C_OR, C_SUB, C_SUBW, C_XOR
CS-type (32 bit version)	C_SW
CS-type (64 bit version)	C_SD
CSS-type (32 bit version)	C_SWSP
CSS-type (64 bit version)	C_SDSP
CB-type	C_BEQZ, C_BNEZ
CJ-type	C_J, C_JAL
CL-type (32 bit version)	C_LW
CL-type (64 bit version)	C_LD

Class Synopsis

Note: This section is under development and will be updated as more classes are implemented.

• Insn: General RISC-V instruction
  • InsnRV32IRType: RV32I R-Type Instruction
    • InsnAdd: ADD instruction
    • InsnSub: SUB instruction
    • InsnSll: SLL instruction
    • InsnSlt: SLT instruction
    • InsnSltu: SLTU instruction
    • InsnXor: XOR instruction
    • InsnSrl: SRL instruction
    • InsnSra: SRA instruction
    • InsnOr: OR instruction
    • InsnAnd: AND instruction

Parameters

TODO