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riscv-formal-nmigen
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Add SUB instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-07 14:00:12 +08:00
parent ccc1bd098b
commit 060dd98919
1 changed files with 11 additions and 0 deletions
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insns/InsnSub.py Normal file
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from InsnRV32IRType import *
class InsnSub(InsnRV32IRType):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011)
def elaborate(self, platform):
m = super(InsnSub, self).elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata - self.rvfi_rs2_rdata, 0))
return m