M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
5,427 Commits 13 Branches 35 Tags 25 MiB
Commit Graph

5427 Commits

Author SHA1 Message Date
Robert Jördens c9b36e3559 conda: bump misoc, close #905 2018-01-25 19:31:26 +01:00
Sebastien Bourdeauducq 0d2f89db53 si5324: chip does not ack RST_REG write 2018-01-25 11:06:19 +08:00
Sebastien Bourdeauducq ca4d5ae73e artiq_flash: add kasli drtio variants 2018-01-25 00:00:07 +08:00
Sebastien Bourdeauducq 77f90cf93b test: relax RTIO counter test and print result 2018-01-24 10:07:22 +08:00
Sebastien Bourdeauducq ed0fbd5662 test: add test for RTIO counter (#883) 2018-01-24 00:28:39 +08:00
Robert Jördens e0e795f11c sayma_amc: constrain pin, remove keep 2018-01-23 15:42:47 +00:00
Robert Jördens ee14912042 conda: bump migen/misoc (vivado constraints) 2018-01-23 16:23:12 +01:00
Robert Jördens b5c035bb52 sayma_rtm: constrain serwb clock input 2018-01-23 13:54:53 +00:00
Robert Jördens aada38f508 kasli, kc705: remove vivado "keep", cleanup a constraint 2018-01-23 13:15:26 +00:00
Robert Jördens 85102e191e sayma_rtm: derive clocks automatically 
* also don't add false paths unless necessary
 2018-01-23 11:00:55 +00:00
Robert Jördens 7d1b3f37c9 sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress 2018-01-23 10:56:42 +00:00
Sebastien Bourdeauducq cb0016ceee examples/sayma: fix ref_multiplier 
SAWG is working, whoohoo!
 2018-01-23 15:26:03 +08:00
Sebastien Bourdeauducq cfffd9e13d si5324: kasli support 2018-01-23 13:17:03 +08:00
Sebastien Bourdeauducq 649deccd9b kasli: fix DRTIO satellite QPLL refclksel 2018-01-23 12:27:19 +08:00
Sebastien Bourdeauducq 4b4374f76a sayma: register_jref for JESD204. Closes #904 2018-01-23 12:19:15 +08:00
Sebastien Bourdeauducq 763aefacff kasli: fix typo 2018-01-23 12:10:54 +08:00
Sebastien Bourdeauducq c7b148a704 kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1 2018-01-23 12:08:10 +08:00
Sebastien Bourdeauducq d6157514c7 gtp_7series: flexible QPLL channel selection 2018-01-23 12:03:09 +08:00
Sebastien Bourdeauducq 9f87c34a94 kasli: fix QPLL instantiation 2018-01-23 10:39:31 +08:00
Sebastien Bourdeauducq 98a5607634 gtp_7series: set clock muxes correctly for second QPLL channel 2018-01-23 10:39:20 +08:00
Sebastien Bourdeauducq 25fee1a0bb gtp_7series: use QPLL second channel 2018-01-23 10:15:49 +08:00
Sebastien Bourdeauducq 031d7ff020 kasli: keep using second QPLL channel for DRTIO satellite 2018-01-23 10:13:10 +08:00
Sebastien Bourdeauducq 626075cbc1 gtp_7series: simplify TX clocking 2018-01-23 09:49:23 +08:00
Robert Jördens 472840f16b conda: bump migen/misoc 
* kasli clock constraint
* vivado false paths
 2018-01-22 20:32:18 +01:00
Robert Jördens 74b7baa8c5 urukul example: mmcx clock input 2018-01-22 20:30:08 +01:00
Robert Jördens a86b28def2 urukul: example additions 
* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
 2018-01-22 20:29:30 +01:00
Robert Jördens 5a9035b122 urukul: faster spi clock 2018-01-22 18:27:40 +00:00
Robert Jördens ca1fdaa190 ad9910: relax timing for faster spi clock 2018-01-22 18:27:40 +00:00
Sebastien Bourdeauducq 0d73401365 conda: bump migen+misoc 2018-01-23 01:28:10 +08:00
Sebastien Bourdeauducq 401e57d41c gtp_7series: fix nchannels assert 2018-01-23 01:28:01 +08:00
Sebastien Bourdeauducq aa62e91487 kasli: add DRTIO targets (no firmware) 2018-01-23 01:27:40 +08:00
Sebastien Bourdeauducq 296ac35f5d sayma_amc: SFP TX disable is active-high 2018-01-23 00:32:09 +08:00
Sebastien Bourdeauducq 77192256ea kc705: style 2018-01-23 00:02:35 +08:00
Sebastien Bourdeauducq ab7c49d6d0 sayma_amc: raise error on invalid variant 2018-01-23 00:02:16 +08:00
Sebastien Bourdeauducq c1ac3b66b1 sayma_rtm: fix 8fe463d4a 2018-01-23 00:01:45 +08:00
Sebastien Bourdeauducq 53facfef13 sayma: build fixes 2018-01-22 18:33:22 +08:00
Sebastien Bourdeauducq 25f3feeda8 refactor targets 2018-01-22 18:25:10 +08:00
Sebastien Bourdeauducq 5198c224a2 sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
whitequark 8598e475e9 artiq_flash: fix a refactoring mistake. 2018-01-20 08:30:42 +00:00
Sebastien Bourdeauducq c3323f0d57 hmc830: improve lock failure error report 2018-01-20 15:42:53 +08:00
whitequark 115aa0d0d6 artiq_flash: support load action for Sayma RTM FPGA. 2018-01-20 07:23:50 +00:00
whitequark 94592c7a4c artiq_flash: unify flash handling in XC7 and Sayma programmers. 2018-01-20 07:23:50 +00:00
whitequark 1ffabac06f artiq_flash: use atexit for tempfile cleanup. 2018-01-20 07:23:50 +00:00
whitequark ab9eb56ceb setup.py: migen now works on Python 3.6, relax version check. 2018-01-20 07:23:50 +00:00
Florent Kermarrec 8fe463d4a0 sayma_rtm: add UART loopback to easily know if rtm fpga is alive 2018-01-20 06:04:34 +01:00
Florent Kermarrec 74ce7319d3 sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?) 2018-01-20 06:04:18 +01:00
whitequark f4022ba872 remoting: avoid a race condition. 2018-01-20 01:30:44 +00:00
whitequark 83278a6edb artiq_flash: fix a refactoring bug. 2018-01-20 01:30:44 +00:00
hartytp 37fa3b29da firmware: add register dump on HMC830 lock timeout. 2018-01-20 00:19:31 +00:00
whitequark 934bc53cb5 artiq_devtool: refactor. 2018-01-19 20:35:35 +00:00