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342 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ec893222a4 rtio: remove support for async mode 2023-01-06 18:22:05 +08:00
Sebastien Bourdeauducq 573a895c1e remove RTIOClockMultiplier 2023-01-06 17:59:18 +08:00
Sebastien Bourdeauducq 5da9794895 remove Sayma and Metlino support 2023-01-06 17:41:12 +08:00
Spaqin 17efc28dbe
DRTIO: RTIO/SYS clock merge 2022-12-17 15:39:54 +08:00
mwojcik ad000609ce simplify tsc with no rtio/sys clk distinction 2022-11-01 08:12:54 +08:00
mwojcik a6856a5e4a rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
Robert Jördens 1820e1f715 phaser: cleanup 2022-10-19 16:25:33 +02:00
Robert Jördens af28bf3550 simplify dt reset 2022-09-08 08:39:48 +02:00
Robert Jördens a91836e5fe easier fix for dt 2022-09-06 20:26:50 +00:00
Robert Jördens 27e3c044ed fix dt computation 2022-09-06 14:32:57 +00:00
Robert Jördens 3809ac5470 fix type, clean clear 2022-09-02 19:47:06 +00:00
Robert Jördens 0df2cadcd3 fixes 2022-09-02 15:29:36 +00:00
Robert Jördens cf48232a90 fixes 2022-09-02 14:38:38 +00:00
Robert Jördens a20087848d differentiate phaser modes 2022-09-02 11:03:23 +00:00
Robert Jördens 47f90a58cc add miqro phy 2022-09-02 09:32:06 +00:00
Spaqin 8be945d5c7
Urukul monitoring (#1142, #1921) 2022-07-07 10:52:53 +08:00
Spaqin 35f30ddf05
Expose TTLClockGen for Kasli JSONs (#1886) 2022-05-06 13:33:42 +08:00
occheung 8da924ec0f dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
Robert Jördens 591507a7c0
Merge pull request #1774 from m-labs/fastino-cic 
Fastino cic
 2021-10-28 17:44:20 +02:00
Robert Jördens 3f6bf33298 fastino: add interpolator support 2021-10-08 15:47:07 +00:00
Spaqin 1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760) 2021-10-07 08:19:38 +08:00
occheung 051a14abf2 rtio/dma: fix endianness 2021-09-10 13:25:12 +08:00
occheung a833974b50 analyzer: fix endianness 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq cf9cf0ab6f ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
Sebastien Bourdeauducq 997a48fb31 ttl_serdes_ultrascale: fix, add dummy dci argument 2021-02-07 22:31:46 +08:00
Sebastien Bourdeauducq bbe0c9162a ttl_serdes_ultrascale: cleanup 2021-02-07 22:00:33 +08:00
Sebastien Bourdeauducq 3572e2a9c7 ttl_serdes_7series: fix 2021-02-07 21:41:13 +08:00
Sebastien Bourdeauducq 88c212b84f ttl_serdes_7series: cleanup 2021-02-07 21:33:21 +08:00
Sebastien Bourdeauducq db25f4e8f7 ttl_serdes_7series: use simpler I/O buffers 
In theory equivalent with these parameters.
 2021-02-07 20:10:37 +08:00
Sebastien Bourdeauducq 6bd9691ba8 gateware: remove TTL dead code 2021-02-07 19:58:02 +08:00
Robert Jördens 30d1acee9f fastlink: fix fastino style link 2020-10-18 20:43:21 +00:00
Robert Jördens 868a9a1f0c phaser: new multidds 2020-09-16 14:06:38 +00:00
Robert Jördens c18f515bf9 phaser: rework rtio channels, sync_dly, init() 2020-09-16 12:23:07 +00:00
Robert Jördens fdd2d6f2fb phaser: SI methods 2020-09-12 11:02:37 +00:00
Robert Jördens 4e24700205 phaser: spelling 2020-09-09 16:52:52 +00:00
Robert Jördens 8aaeaa604e phaser: share_lut 2020-09-07 16:06:35 +00:00
Robert Jördens 272dc5d36a phaser: documentation 2020-08-28 16:36:44 +00:00
Robert Jördens 96fc248d7c phaser: synchronize multidds to frame 2020-08-27 14:28:19 +00:00
Robert Jördens c10ac2c92a phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb) 2020-08-27 14:26:09 +00:00
Robert Jördens e5e2392240 phaser: wire up multidds 2020-08-26 17:12:41 +00:00
Robert Jördens d1be1212ab phaser: coredevice shim, dds [wip] 2020-08-26 15:10:50 +00:00
Robert Jördens 20fcfd95e9 phaser: coredevice shim, readback fix 2020-08-24 15:46:31 +00:00
Robert Jördens bcefb06e19 phaser: ddb template, split crc 2020-08-24 14:51:50 +00:00
Robert Jördens 11c9def589 phaser: readback delay, test fastlink 2020-08-24 14:49:36 +00:00
Robert Jördens 63e4b95325 fastlink: rework crc injection 2020-08-23 19:41:13 +00:00
Robert Jördens a27a03ab3c fastlink: fix crc vs data width 2020-08-23 19:02:50 +00:00
Robert Jördens 7e584d0da1 fastino: use fastlink 2020-08-22 11:56:23 +00:00
Robert Jördens 3e99f1ce5a phaser: refactor link 2020-08-22 11:56:23 +00:00
Robert Jördens a34a647ec4 phaser: refactor fastlink 2020-08-22 11:56:23 +00:00
Robert Jördens aa0154d8e2 phaser: initial 2020-08-22 11:56:23 +00:00