994ceca9ff
sayma_amc: disable slave fpga gateware loading
2018-03-06 17:27:43 +01:00
f4dad87fd9
coredevice: add pcf8574a driver
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I2C IO expander with 8 quasi-bidirectional pins
2018-03-06 14:27:19 +01:00
62af7fe2ac
Revert "kasli/opticlock: use plain ttls for channels 8-23"
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This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.
No decrease in power consumption or improvement in timing.
2018-03-06 14:27:19 +01:00
fd3cdce59a
kasli/opticlock: use plain ttls for channels 8-23
2018-03-06 14:27:19 +01:00
50298a6104
ttl_serdes_7series: suppress diff_term in outputs
2018-03-06 14:27:19 +01:00
e356150ac4
ttl_simple: support differential io
2018-03-06 14:27:19 +01:00
956098c213
kasli: add second urukul, make clk_sel drive optional
2018-03-06 14:26:27 +01:00
07de7af86a
kasli: make second eem optional in urukul
2018-03-06 14:26:26 +01:00
257bef0d21
slave_fpga: print more info
2018-03-06 14:26:26 +01:00
c25560baec
sed: more LaneDistributor comments
2018-03-06 20:56:35 +08:00
f40255c968
sed: add comments about key points in LaneDistributor
2018-03-06 20:51:09 +08:00
Florent Kermarrec
5b3d6d57e2
drtio/gth: power down rx on restart (seems to make link initialization reliable)
2018-03-06 11:49:28 +01:00
Florent Kermarrec
64b05f07bb
drtio/gth: use parameters from Xilinx transceiver wizard
2018-03-06 11:02:15 +01:00
Florent Kermarrec
45f1e5a70e
drtio/gth: cleanup import
2018-03-06 10:56:07 +01:00
a274af77d5
runtime: fix compilation without DRTIO
2018-03-05 00:43:42 +08:00
432e61bbb4
drtio: add kernel API to check for link status. Closes #941
2018-03-05 00:23:55 +08:00
6aaa8bf9d9
drtio: fix link error generation
2018-03-04 23:20:13 +08:00
d747d74cb3
test: fix test_dma
2018-03-04 23:19:06 +08:00
928d5dc9b3
drtio: raise RTIOLinkError if operation fails due to link lost ( #942 )
2018-03-04 01:02:53 +08:00
ba74013e3e
runtime: add a missing overflow flag reset
2018-03-03 13:16:21 +08:00
abfbadebb5
doc: DMA can also raise RTIOUnderflow
2018-03-03 13:14:34 +08:00
ddcc68cff9
sayma_amc: move bitstream options to migen
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close #930
2018-03-02 18:13:03 +08:00
5e074f83ac
examples: update kasli sysu
2018-03-02 16:05:12 +08:00
29d42f4648
artiq_flash: add kasli sysu
2018-03-02 15:49:41 +08:00
a9daaad77b
kasli: add SYSU variant and device_db
2018-03-02 14:44:31 +08:00
1c57d27ae2
slave_fpga: use sayma_rtm magic
2018-03-01 18:32:19 +01:00
de63e657b8
kasli/si5324: lock to 100 MHz with highest available bandwidth
2018-03-01 14:49:53 +01:00
abd160d143
slave_fpga: check DONE before loading
2018-03-01 19:53:34 +08:00
a04a36ee36
firmware: move wait for write completion to read()
2018-03-01 11:37:33 +01:00
a6ae08d8b8
firmware/spi: work around cs_polarity semantics
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The semantics differ between the RTIO and CSR interface.
2018-03-01 11:19:18 +01:00
cc70578f1f
remove old spi RTIO Phy
2018-03-01 11:19:18 +01:00
ec5b81da55
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
6fbe0d8ed8
hmc830: be explicit about SPI mode selection
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
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* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
68278e225d
slave_fpga: check for INIT low
2018-03-01 17:28:01 +08:00
whitequark
14f6fa6699
firmware: fix a warning.
2018-03-01 01:25:55 +00:00
whitequark
d051cec0dd
firmware: remove useless module.
2018-03-01 01:22:52 +00:00
54984f080b
artiq_flash: flash RTM firmware
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based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:29:01 +01:00
0c49201be7
firmware: add slave fpga serial load support
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based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:27:52 +01:00
1f999c7f5f
sayma_amc: expose RTM fpga load pins as GPIOs
2018-02-28 18:44:36 +01:00
cedecc3030
Revert "firmware: Sayma RTM FPGA bitstream loading prototype ( #813 )."
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This reverts commit f95fb273f1
2018-02-28 18:43:56 +01:00
whitequark
f95fb273f1
firmware: Sayma RTM FPGA bitstream loading prototype ( #813 ).
2018-02-28 16:46:23 +00:00
Florent Kermarrec
2896dc619b
drtio/transceiver/gth: fix multilane
2018-02-28 14:15:40 +01:00
5046d6a529
ad9912/10: add a bit more slack to init()
2018-02-27 23:14:44 +01:00
f97163cdee
examples/master: sync device_db with kc705_nist_clock
2018-02-27 19:40:00 +01:00
whitequark
916b10ca94
examples: spi → spi2.
2018-02-27 18:36:45 +00:00
386aa75aaa
kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master
2018-02-27 23:18:18 +08:00
5d81877b34
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
2018-02-27 23:15:20 +08:00
Florent Kermarrec
1f0d955ce4
drtio/transceiver/gtp: implement tx multi lane phase alignment sequence
2018-02-27 12:32:25 +01:00
e565d3fa59
kasli: add analyzer and RTIO log to DRTIO master target
2018-02-27 18:09:07 +08:00
760724c500
kasli/device_db: fix i2c switch addr
2018-02-26 11:37:12 +01:00
b466a569bf
coredevice: export spi2
2018-02-24 09:49:31 +01:00
Florent Kermarrec
5b0f9cc6fd
drtio/transceiver/gth: fix single transceiver case
2018-02-23 12:15:47 +01:00
cff85ee13b
novogorny: simplify and fix coefficient
2018-02-23 10:09:44 +01:00
Florent Kermarrec
b4ba71c7a4
drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...)
2018-02-23 08:37:05 +01:00
Florent Kermarrec
820c834251
drtio/transceiver/gth: implement tx multi lane phase alignment sequence
2018-02-22 22:14:15 +01:00
bc5e949bb4
novogorny: fix gain register length
2018-02-22 18:45:55 +00:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
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m-labs/artiq#687
2018-02-22 17:19:51 +01:00
74517107f0
ad9912: add slack after prodid read
2018-02-22 17:19:51 +01:00
3b7971d15d
kasli: spelling
2018-02-22 17:19:51 +01:00
771bf87b56
kc705: port amc101_dac/spi0 and sma_spi to spi2
2018-02-22 17:19:51 +01:00
d4a10dcbd4
urukul: fix example
2018-02-22 11:28:50 +01:00
e8d4db1ccf
coreanalyzer: add spi2 support
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m-labs/artiq#926
2018-02-22 11:28:46 +01:00
f8e6b4f4e3
ad5360: port to spi2
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* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
96423882f2
fix 4d6619f3b
2018-02-22 15:27:54 +08:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
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Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
4d6619f3bc
satman: send ResetAck
2018-02-22 15:17:44 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
898bad5abc
spi2: fixes
2018-02-21 19:41:05 +01:00
Florent Kermarrec
5eda894db4
firmware/libboard/sdram: increase read_delays dead zone to 32 on KU
2018-02-21 19:36:37 +01:00
whitequark
96f697ec96
firmware: update compiler_builtins to unbreak __gtdf2.
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Fixes #883 .
2018-02-21 15:21:48 +00:00
a63fd306af
urukul: use spi2
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* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
37a0d6580b
spi2: add RTIO gateware and coredevice driver
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1006218997
2018-02-21 13:37:36 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7a1d71502a
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
2018-02-21 13:37:29 +00:00
476e4fdd56
ttl_serdes_7series: disable IBUF and INTERM when output
2018-02-21 13:37:29 +00:00
Florent Kermarrec
afc16a67b6
firmware/liboard/sdram.rs: iterate read multiple times in read_delays to avoid false positives
2018-02-21 14:15:35 +01:00
whitequark
86ceee570f
compiler: reject calls with unexpected keyword arguments.
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Fixes #924 .
2018-02-21 11:37:12 +00:00
f060d6e1b3
drtio: increase A7 clock aligner check period
2018-02-20 18:50:35 +08:00
738654c783
drtio: support remote RTIO resets
2018-02-20 18:48:54 +08:00
f15b4bdde7
style
2018-02-20 18:47:59 +08:00
7d9c7ada71
drtio: fix test infinite loop
2018-02-20 17:42:00 +08:00
ad2c9590d0
drtio: rewrite/fix reset and link bringup/teardown
2018-02-20 17:26:43 +08:00
7e02d8245c
kasli: false paths
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* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
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Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
52049cf36a
drtio: add Xilinx RX synchronizer
2018-02-19 17:49:43 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
Florent Kermarrec
f5831af535
drtio/transceiver/gtp_7series_init: don't reset gtp rx on power down
2018-02-19 10:03:19 +01:00
Florent Kermarrec
89a158c0c9
drtio/transceiver/gtp_7series_init: remove dead code
2018-02-19 10:02:23 +01:00
Florent Kermarrec
782051f474
drtio/transceiver/gtp_7series_init: add no retiming on gtp resets
2018-02-19 09:59:50 +01:00
01fa6c1c2e
reorganize examples
2018-02-19 15:46:08 +08:00
4b4090518b
drtio: clean up remnants of removed debug functions
2018-02-19 15:14:32 +08:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
94c20dfd4d
drtio: fix misleading GenericRXSynchronizer comment
2018-02-19 00:47:54 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
c87636ed2b
si5324: fix cfb21ca
2018-02-18 11:38:20 +01:00
