M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

novogorny: fix gain register length

Browse Source
This commit is contained in:
Robert Jördens 2018-02-22 18:45:55 +00:00
parent 1452cd7447
commit bc5e949bb4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/coredevice/novogorny.py
View File

@ -100,7 +100,7 @@ class Novogorny:
self.gains &= ~(0b11 << (channel*2))
self.gains |= gain << (channel*2)
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END,
2, self.div, SPI_CS_SR)
16, self.div, SPI_CS_SR)
self.bus.write(self.gains << 16)
@kernel