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spi2: fixes
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@ -7,9 +7,7 @@ Output event replacement is not supported and issuing commands at the same
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time is an error.
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"""
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from numpy import int64
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from artiq.language.core import syscall, kernel, portable, now_mu, delay_mu
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from artiq.language.types import TInt32, TNone
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -72,11 +70,10 @@ class SPIMaster:
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@portable
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def frequency_to_div(self, f):
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"""Convert a SPI clock frequency to the closest SPI clock divider."""
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return int64(round(
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1/(f*self.core.mu_to_seconds(self.ref_period_mu))))
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return int(round(1/(f*self.core.mu_to_seconds(self.ref_period_mu))))
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@kernel
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def set_config(self, flags, length, freq, c):
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def set_config(self, flags, length, freq, cs):
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"""Set the configuration register.
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* If ``SPI_CS_POLARITY`` is cleared (``cs`` active low, the default),
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@ -140,8 +137,7 @@ class SPIMaster:
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Or number of the chip select to assert if ``cs`` is decoded
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downstream. (reset=0)
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"""
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self.set_config_mu(
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flags, length, self.frequency_to_div(write_freq), cs)
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self.set_config_mu(flags, length, self.frequency_to_div(freq), cs)
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@kernel
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def set_config_mu(self, flags, length, div, cs):
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