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668 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 6e0288e568 drtio: fix GTH CPLL reset 2017-12-30 12:14:36 +08:00
Robert Jördens 379d29561b sayma: plausibility assertion on sawg data stream 2017-12-29 19:15:40 +01:00
Robert Jördens 37f9c0b10c spi: register clk 
following m-labs/misoc#65
1dc68b0d0b
 2017-12-28 16:50:22 +01:00
whitequark acd13837ff firmware: implement the new bootloader. 2017-12-28 13:18:51 +00:00
Sebastien Bourdeauducq 8153cfa88f drtio/gth: add probes on {tx,rx}_init.done 2017-12-28 16:49:08 +08:00
Sebastien Bourdeauducq c086149782 drtio/gth: use async microscope probes 2017-12-28 16:37:40 +08:00
whitequark d94db1de5d Revert accidentally committed parts of 1b9b5602. 2017-12-28 08:23:34 +00:00
whitequark 1b9b560242 firmware: use libbuild_misoc in libdrtioaux. NFC. 2017-12-28 08:20:23 +00:00
Sebastien Bourdeauducq 6801921fc0 drtio: instrument GTH transceiver 2017-12-28 15:03:14 +08:00
Sebastien Bourdeauducq 70b7f28ad3 drtio: drive SFP TX disable pins 2017-12-23 22:58:51 +08:00
Sebastien Bourdeauducq f8c8f3fe26 drtio: fix GTH clock domains 2017-12-23 07:21:44 +08:00
Sebastien Bourdeauducq 1af21c0b29 drtio: integrate GTH transceiver for Sayma 2017-12-23 01:19:59 +08:00
Sebastien Bourdeauducq c57b66497c drtio: refactor/simplify GTH, use migen 2017-12-23 01:19:44 +08:00
Sebastien Bourdeauducq 77897228ca drtio: add GTH transceiver code from Florent (197c79d47) 2017-12-22 18:01:28 +08:00
Sebastien Bourdeauducq ebdbaaad32 drtio: remove KC705/GTX support 2017-12-22 17:51:42 +08:00
Sebastien Bourdeauducq 0681d472c7 conda: fix sayma_rtm_csr.csv location for Sayma AMC 2017-12-22 17:14:10 +08:00
Sebastien Bourdeauducq 44959144d8 conda: add Sayma AMC standalone board package 2017-12-22 16:44:04 +08:00
Florent Kermarrec 86825a852c gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200 2017-12-21 23:52:44 +01:00
Sebastien Bourdeauducq a6ffe9f38d drtio: add Sayma top-level designs 2017-12-21 23:08:56 +08:00
Sebastien Bourdeauducq 4fbc8772a5 sayma: allocate all user LEDs to RTIO, make one TTL SMA input 2017-12-21 19:27:38 +08:00
Sebastien Bourdeauducq a23251276d Revert "sayma: set up Si5324 for RGMII clock rerouting" 
This reverts commit 2b01aa22b6.
 2017-12-21 14:42:15 +08:00
Sebastien Bourdeauducq 2b01aa22b6 sayma: set up Si5324 for RGMII clock rerouting 2017-12-17 00:25:33 +08:00
Sebastien Bourdeauducq b6199bb35b sayma: style 2017-12-15 19:45:51 +08:00
Sebastien Bourdeauducq 649b60ea29 targets/kc705_drtio: remove DAC FMC card support 2017-12-15 17:32:25 +08:00
Sebastien Bourdeauducq 341e809859 targets/sayma_rtm: enable Allaki RF switches, GPIO access to attenuator 2017-12-15 13:08:35 +08:00
Sebastien Bourdeauducq 569484f888 remove phaser, adapt SAWG example to Sayma 2017-12-14 18:49:27 +08:00
Robert Jördens 5e251cd85c sayma_amc: remove redundant bitstream options 
* CONFIGRATE default is sufficient
* SPI width can be auto and QSPI works
 2017-12-13 14:39:32 +01:00
Robert Jördens a9d0f253a5 sayma_amc: set bitstream and config parameters 
* slow down CCLK rate as there is additional loading
  on the signals
* single bit SPI for now until we know that quad SPI
  works
* set up

https://github.com/m-labs/artiq/issues/847
 2017-12-13 21:21:52 +08:00
whitequark 1c25f7ef52 gateware: make software builds spew less junk on the console. 
[ci skip]
 2017-12-04 14:19:35 +00:00
Sebastien Bourdeauducq bb3d6ef84a sayma: remove ad9154 from mem_map 
Address is autogenerated by CSR system.
 2017-11-29 18:17:25 +08:00
Robert Jördens ecfe2e40ee sayma_amc_standalone: rtio channels for both sawg groups 2017-11-19 18:32:42 +01:00
Robert Jördens d1a7c1c3a1 sayma_amc_standalone: connect sawg to jesd again 2017-11-19 14:36:20 +01:00
Florent Kermarrec dfdd2dd9e6 gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb 2017-11-19 09:01:20 +01:00
Florent Kermarrec cd83b71d92 gateware/targets/sayma_amc_standalone: serwb working, need fixing on AD9154 data mapping 2017-11-18 18:10:28 +01:00
Florent Kermarrec f003566e52 serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue... 
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
 2017-11-18 18:01:46 +01:00
Florent Kermarrec 1b976bfa4d gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x 2017-11-18 17:57:11 +01:00
Florent Kermarrec 464b24a608 gateware/targets/sayma_amc: integrate ad9154 correctly (add crg, use cpll instead of qpll, use correct clocking) and cleanup serwb constraints. 2017-11-10 10:48:32 +01:00
Florent Kermarrec 278c739d30 gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints 2017-11-10 10:39:47 +01:00
Florent Kermarrec 48bfaec8d3 gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8 2017-11-10 10:37:08 +01:00
Florent Kermarrec 59be095512 gateware/serwb/kusphy: use locally inverted clk_b on iserdese3 2017-11-10 10:35:48 +01:00
Florent Kermarrec db82b11f29 gateware/serwb/core: cleanup and increase fifo depth 2017-11-10 10:33:39 +01:00
Florent Kermarrec 76ddb063cf gateware/targets/sayma: get hmc830/7043 spi working (still need to test clock generation) 2017-11-06 12:08:28 +01:00
Florent Kermarrec 5bd1e43ced gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
Sebastien Bourdeauducq d80cf8d59d kc705: add TTLs and shift register driver for FMC DIO 2017-10-31 23:14:39 +08:00
Sebastien Bourdeauducq d5b5076f67 gateware/ad5360_monitor: fix SPI data decoding 2017-10-26 11:58:59 +08:00
Sebastien Bourdeauducq 412548a86c gateware: add AD5360 monitor (untested) 2017-10-23 20:09:28 +08:00
Sebastien Bourdeauducq 5803ac9998 gateware: add Zotino SPI to NIST CLOCK target 2017-10-23 15:04:30 +08:00
Sebastien Bourdeauducq 4fa823b62a gateware: add support for SPI-over-LVDS 2017-10-23 15:04:01 +08:00
Robert Jördens c7de233208 Merge Sayma SAWG changes (untested) 
See #798

* sinara:
  conda: bump migen
  sayma_amc: SAWG (untested)
  sayma_rtm: make build dir
  conda: jesd204b 0.4
 2017-09-29 21:01:02 +02:00
Sebastien Bourdeauducq b4c52c34f7 Merge branch 'sinara' 2017-09-30 01:11:16 +08:00