2b0d63db23
hmc830_7043: support 125MHz RTIO
2019-01-28 13:44:08 +08:00
bdd4e52a53
ad9154: support 125MHz RTIO
2019-01-28 13:43:52 +08:00
47312e55d3
sayma: set RTIO_FREQUENCY in MasterDAC
2019-01-28 13:43:28 +08:00
443d6d8688
sayma_amc: pass RTIO clock frequency to SiPhaser
2019-01-28 09:49:03 +08:00
3b6f47886e
firmware: print more info on DDMTD stability error
2019-01-27 23:06:11 +08:00
74fdd04622
firmware: test DDMTD stability
2019-01-27 20:39:12 +08:00
81b0046f98
ddmtd: add deglitchers
2019-01-27 20:38:41 +08:00
8254560577
sayma: properly determine SYSREF coarse calibration target
2019-01-27 16:00:36 +08:00
214394e3b0
sayma: reimplement DAC SYSREF autocalibration
2019-01-27 15:28:39 +08:00
fdbf1cc2b2
sayma: rework DAC SYSREF margin validation
...
Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
2019-01-27 14:17:54 +08:00
7e5c062c2c
firmware: bypass channel divider for HMC7043 DCLK
2019-01-27 11:49:34 +08:00
f73ffe44f9
firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)
...
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.
Needs cleanup and optimization/characterization.
2019-01-27 09:51:24 +08:00
8632b553d2
ddmtd: use IOB register to sample input
2019-01-27 09:50:02 +08:00
d1ef036948
kasli_sawgmaster: initialize SAWG phase according to RTIO TSC
2019-01-27 09:49:31 +08:00
9966e789fc
sayma: simplify Ultrascale LVDS T false path
...
Recommended by Xilinx.
2019-01-25 23:40:48 +08:00
359fb1f207
sayma: fix DDMTD STA
2019-01-25 23:39:19 +08:00
cb04230f86
sayma: SYSREF setup/hold validation demonstration
...
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
...
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
cc9420d2c8
hmc7043: fix divider programming
2019-01-25 11:48:50 +08:00
8c5a502591
ad53xx: ignore F3 (reserved)
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-24 15:50:46 +01:00
bbac92442f
sayma: check hmc7043 slip period
2019-01-24 20:13:43 +08:00
a92cc91dcb
kasli_sawgmaster: correctly tune DDS and SAWG
2019-01-24 19:37:14 +08:00
f8b39b0b9a
sayma: enable 2X DAC interpolation
...
Seems to work just fine and gets one clock divider out of the way.
2019-01-24 18:28:01 +08:00
07b5b0d36d
kasli: adapt Master target to new hardware
2019-01-24 18:27:15 +08:00
31592fc8e4
nix: install flash proxy bitstreams with OpenOCD
2019-01-24 16:47:37 +08:00
0a0e8c3c93
nix: bump migen/misoc
2019-01-24 16:20:02 +08:00
3917a0ef46
nix: support reusing dev environment in build scripts
2019-01-23 21:59:39 +08:00
154269b77a
kasli: fix HUST satellite Urukul
2019-01-23 17:59:43 +08:00
3b5fd3ac11
kasli_tester: fix grabber test
2019-01-23 17:59:25 +08:00
330c5610e9
ad9912: fix imports
2019-01-23 17:59:08 +08:00
390f05f762
firmware: use smoltcp release
2019-01-23 16:15:05 +08:00
d7e6f104d2
kasli: add HUST variants
2019-01-23 14:11:51 +08:00
81f2b2c864
kasli: remove unpopulated Tester EEMs
...
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
2019-01-23 12:14:44 +08:00
01f1df7e50
nix: fix version strings in artiq-dev environment
2019-01-23 11:21:09 +08:00
b692981c8e
ad9910: add note about red front panel led
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 12:49:42 +01:00
a0eba5b09b
satman: support Grabber
2019-01-22 19:36:13 +08:00
2e3555de85
firmware: fix compilation error with more than 1 Grabber
2019-01-22 19:35:46 +08:00
9ee5fea88d
kasli: support optional SATA port for DRTIO
2019-01-22 18:06:48 +08:00
91e375ce6a
ad9910: don't reset the input divide-by-two
...
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221 ;
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 09:37:20 +00:00
2174935231
nix: update package descriptions
2019-01-22 15:06:42 +08:00
81ff3d4b29
ad9912: add some slack after init
2019-01-21 17:10:58 +00:00
4869636a55
nix: remove broken version strings
2019-01-21 23:55:25 +08:00
79ffd1e0bf
nix: enable pythonparser and artiq unittests
2019-01-21 23:42:10 +08:00
a9678dd9f2
test_frontends: always skip GUI programs
...
The "import PyQt5" hack breaks on nix/hydra.
2019-01-21 23:41:07 +08:00
e024fa89e5
nix: disable maintainer entries for now
...
Causes problem with hydra when building against release nixpkgs,
where the sb0 maintainer entry is not present yet.
2019-01-21 22:53:57 +08:00
84f7d006e8
ad9910: add precision about tune_io_update_delay/tune_sync_delay order
2019-01-21 19:40:55 +08:00
30051133b7
urukul: fix typos
2019-01-21 19:40:55 +08:00
30b2f54baa
kasli_tester: skip Zotino test when no Zotino is present
2019-01-21 18:11:41 +08:00
bff8c8cb05
kasli: add Berkeley variant
2019-01-21 17:44:17 +08:00
