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hmc830_7043: support 125MHz RTIO
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@ -163,10 +163,10 @@ pub mod hmc7043 {
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// Warning: dividers are not synchronized with HMC830 clock input!
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// Set DAC_CLK_DIV to 1 or 0 for deterministic phase.
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// (0 bypasses the divider and reduces noise)
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pub const DAC_CLK_DIV: u16 = 0; // 2400MHz
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pub const FPGA_CLK_DIV: u16 = 16; // 150MHz
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pub const SYSREF_DIV: u16 = 256; // 9.375MHz
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const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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pub const DAC_CLK_DIV: u16 = 0;
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pub const FPGA_CLK_DIV: u16 = 16;
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pub const SYSREF_DIV: u16 = 256;
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const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // must be <= 4MHz
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// enabled, divider, output config
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const OUTPUT_CONFIG: [(bool, u16, u8); 14] = [
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@ -413,17 +413,26 @@ pub mod hmc7043 {
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}
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pub fn init() -> Result<(), &'static str> {
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// used by MasterDAC - HMC830 is clocked from 100MHz reference
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#[cfg(all(hmc830_ref = "100", rtio_frequency = "125.0"))]
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const DIV: (u32, u32, u32, u32) = (1, 20, 0, 1); // 100MHz -> 2.0GHz
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#[cfg(all(hmc830_ref = "100", rtio_frequency = "150.0"))]
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const DIV: (u32, u32, u32, u32) = (1, 24, 0, 1); // 100MHz -> 2.4GHz
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// used by Satellite - HMC830 is clocked by recovered clock
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// (or a clock of the same frequency derived from the same oscillator)
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#[cfg(all(hmc830_ref = "125", rtio_frequency = "125.0"))]
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const DIV: (u32, u32, u32, u32) = (2, 32, 0, 1); // 125MHz -> 2.0GHz
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#[cfg(all(hmc830_ref = "150", rtio_frequency = "150.0"))]
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const DIV: (u32, u32, u32, u32) = (2, 32, 0, 1); // 150MHz -> 2.4GHz
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clock_mux::init();
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/* do not use other SPI devices before HMC830 SPI mode selection */
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hmc830::select_spi_mode();
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hmc830::detect()?;
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hmc830::init();
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// 2.4GHz out
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#[cfg(hmc830_ref = "100")]
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hmc830::set_dividers(1, 24, 0, 1);
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#[cfg(hmc830_ref = "150")]
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hmc830::set_dividers(2, 32, 0, 1);
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hmc830::set_dividers(DIV.0, DIV.1, DIV.2, DIV.3);
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hmc830::check_locked()?;
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