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urukul: fix typos
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@ -615,7 +615,7 @@ class AD9910:
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This method first locates a valid SYNC_IN delay at zero validation
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window size (setup/hold margin) by scanning around `search_seed`. It
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then looks for similar valid delays at successively larger validation
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window sizes until none can be found. It then deacreses the validation
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window sizes until none can be found. It then decreases the validation
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window a bit to provide some slack and stability and returns the
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optimal values.
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@ -340,7 +340,7 @@ class CPLD:
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and align it to the current RTIO timestamp.
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The SYNC_IN signal is derived from the coarse RTIO clock
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and the divider must be a power of two two.
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and the divider must be a power of two.
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Configure ``sync_sel == 0``.
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:param div: SYNC_IN frequency divider. Must be a power of two.
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