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ad9910: add note about red front panel led

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Signed-off-by: Robert Jördens <rj@quartiq.de>
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Robert Jördens 2019-01-22 11:49:09 +00:00
parent a0eba5b09b
commit b692981c8e
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artiq/coredevice/ad9910.py
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@ -79,6 +79,7 @@ class AD9910:
clk_div is the reference clock divider (both set in the parent
Urukul CPLD instance).
:param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
Note that when bypassing the PLL the red front panel LED may remain on.
:param pll_cp: DDS PLL charge pump setting.
:param pll_vco: DDS PLL VCO range selection.
:param sync_delay_seed: SYNC_IN delay tuning starting value.