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6947 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
Robert Jördens 90c9fa446f test: add array transfer test 
200 kB/s, more than a factor of 10 slower than the bare string transfer

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-28 14:30:44 +00:00
Sebastien Bourdeauducq 7a5d28b73d jesd204sync: test SYSREF period 2019-01-28 19:11:38 +08:00
Sebastien Bourdeauducq 1a42e23fb4 jesd204sync: print DDMTD SYSREF final alignment delta 2019-01-28 18:39:16 +08:00
Sebastien Bourdeauducq eebff6d77f jesd204sync: fix max_phase_deviation 2019-01-28 18:38:18 +08:00
Sebastien Bourdeauducq b9e3fab49c jesd204sync: improve messaging 2019-01-28 18:37:46 +08:00
Sebastien Bourdeauducq 145f08f3fe jesd204sync: update SYSREF S/H limit deviation tolerance 
Follows the increased DDMTD resolution.
 2019-01-28 18:21:31 +08:00
Sebastien Bourdeauducq ba21dc8498 jesd204sync: improve messaging 2019-01-28 18:08:20 +08:00
Sebastien Bourdeauducq 3acee87df2 firmware: improve DDMTD resolution using dithering/averaging 2019-01-28 16:04:04 +08:00
Sebastien Bourdeauducq cfe66549ff jesd204sync: cleanup DDMTD averaging code 2019-01-28 14:14:50 +08:00
Sebastien Bourdeauducq 2b0d63db23 hmc830_7043: support 125MHz RTIO 2019-01-28 13:44:08 +08:00
Sebastien Bourdeauducq bdd4e52a53 ad9154: support 125MHz RTIO 2019-01-28 13:43:52 +08:00
Sebastien Bourdeauducq 47312e55d3 sayma: set RTIO_FREQUENCY in MasterDAC 2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq 443d6d8688 sayma_amc: pass RTIO clock frequency to SiPhaser 2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq 3b6f47886e firmware: print more info on DDMTD stability error 2019-01-27 23:06:11 +08:00
Sebastien Bourdeauducq 74fdd04622 firmware: test DDMTD stability 2019-01-27 20:39:12 +08:00
Sebastien Bourdeauducq 81b0046f98 ddmtd: add deglitchers 2019-01-27 20:38:41 +08:00
Sebastien Bourdeauducq 8254560577 sayma: properly determine SYSREF coarse calibration target 2019-01-27 16:00:36 +08:00
Sebastien Bourdeauducq 214394e3b0 sayma: reimplement DAC SYSREF autocalibration 2019-01-27 15:28:39 +08:00
Sebastien Bourdeauducq fdbf1cc2b2 sayma: rework DAC SYSREF margin validation 
Previous code did not work when delay range was not enough for two rotations.
This removes autocalibration, to be done later. Uses hardcoded value for now.
 2019-01-27 14:17:54 +08:00
Sebastien Bourdeauducq 7e5c062c2c firmware: bypass channel divider for HMC7043 DCLK 2019-01-27 11:49:34 +08:00
Sebastien Bourdeauducq f73ffe44f9 firmware: implement DDMTD-based SYSREF/RTIO alignment (draft) 
Mostly works and usually gets the DAC synchronized at 2.4GHz with Urukul across DRTIO.

Needs cleanup and optimization/characterization.
 2019-01-27 09:51:24 +08:00
Sebastien Bourdeauducq 8632b553d2 ddmtd: use IOB register to sample input 2019-01-27 09:50:02 +08:00
Sebastien Bourdeauducq d1ef036948 kasli_sawgmaster: initialize SAWG phase according to RTIO TSC 2019-01-27 09:49:31 +08:00
Sebastien Bourdeauducq 9966e789fc sayma: simplify Ultrascale LVDS T false path 
Recommended by Xilinx.
 2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq 359fb1f207 sayma: fix DDMTD STA 2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq cb04230f86 sayma: SYSREF setup/hold validation demonstration 
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
 2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq 3356717316 sayma: DDMTD SYSREF measurement demonstration 2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq 4941fb3300 sayma: 2.4GHz DAC clocking (4X interpolation) 
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
 2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq cc9420d2c8 hmc7043: fix divider programming 2019-01-25 11:48:50 +08:00
Robert Jördens 8c5a502591 ad53xx: ignore F3 (reserved) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-24 15:50:46 +01:00
Sebastien Bourdeauducq bbac92442f sayma: check hmc7043 slip period 2019-01-24 20:13:43 +08:00
Sebastien Bourdeauducq a92cc91dcb kasli_sawgmaster: correctly tune DDS and SAWG 2019-01-24 19:37:14 +08:00
Sebastien Bourdeauducq f8b39b0b9a sayma: enable 2X DAC interpolation 
Seems to work just fine and gets one clock divider out of the way.
 2019-01-24 18:28:01 +08:00
Sebastien Bourdeauducq 07b5b0d36d kasli: adapt Master target to new hardware 2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq 31592fc8e4 nix: install flash proxy bitstreams with OpenOCD 2019-01-24 16:47:37 +08:00
Sebastien Bourdeauducq 0a0e8c3c93 nix: bump migen/misoc 2019-01-24 16:20:02 +08:00
Sebastien Bourdeauducq 3917a0ef46 nix: support reusing dev environment in build scripts 2019-01-23 21:59:39 +08:00
Sebastien Bourdeauducq 154269b77a kasli: fix HUST satellite Urukul 2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq 3b5fd3ac11 kasli_tester: fix grabber test 2019-01-23 17:59:25 +08:00
Sebastien Bourdeauducq 330c5610e9 ad9912: fix imports 2019-01-23 17:59:08 +08:00
Sebastien Bourdeauducq 390f05f762 firmware: use smoltcp release 2019-01-23 16:15:05 +08:00
Sebastien Bourdeauducq d7e6f104d2 kasli: add HUST variants 2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq 81f2b2c864 kasli: remove unpopulated Tester EEMs 
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
 2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq 01f1df7e50 nix: fix version strings in artiq-dev environment 2019-01-23 11:21:09 +08:00
Robert Jördens b692981c8e ad9910: add note about red front panel led 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 12:49:42 +01:00
Sebastien Bourdeauducq a0eba5b09b satman: support Grabber 2019-01-22 19:36:13 +08:00
Sebastien Bourdeauducq 2e3555de85 firmware: fix compilation error with more than 1 Grabber 2019-01-22 19:35:46 +08:00
Sebastien Bourdeauducq 9ee5fea88d kasli: support optional SATA port for DRTIO 2019-01-22 18:06:48 +08:00
Robert Jördens 91e375ce6a ad9910: don't reset the input divide-by-two 
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221;

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 09:37:20 +00:00