M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity
7,062 Commits 18 Branches 34 Tags 36 MiB
Commit Graph

1338 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ef1871bcea gateware: remove wrpll 
Will be part of ARTIQ-6.
 2019-11-14 17:30:10 +08:00
David Nadlinger bc3b55b1a8 gateware/eem: Force IOB=TRUE on Urukul SYNC output 
Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.

(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
 2019-11-05 17:14:07 +08:00
Sebastien Bourdeauducq 98854473dd sayma_amc: use all transceivers on master (#1230) 2019-11-02 12:12:32 +08:00
Sebastien Bourdeauducq 42af76326f kasli: enlarge integrated CPU SRAM for DRTIO masters 
Required by the bootloader netboot support.
 2019-11-01 10:15:13 +08:00
Sebastien Bourdeauducq 228e44a059 sayma: enable Ethernet on DRTIO satellite variant 
So that netboot can be used in bootloader.
 2019-10-30 21:39:00 +08:00
Sebastien Bourdeauducq dc71039934 sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants 2019-10-30 21:36:00 +08:00
Sebastien Bourdeauducq 462cf5967e bootloader: add netboot support 2019-10-30 21:23:42 +08:00
Sebastien Bourdeauducq 8fa3c6460e sayma_amc: set direction of external TTL buffer according to RTIO PHY OE 2019-10-16 18:48:50 +08:00
Sebastien Bourdeauducq 37d0a5dc19 rtio/ttl: expose OE 2019-10-16 18:48:20 +08:00
Sebastien Bourdeauducq bc060b7f01 style 2019-10-16 18:18:11 +08:00
Sebastien Bourdeauducq 21a1c6de3f sayma: use SFP0 for DRTIO master 2019-10-16 17:53:40 +08:00
Sebastien Bourdeauducq 314d9b5d06 kasli: default to 125MHz frequency for DRTIO 
This is the consistent and most common option. Sayma will also eventually move to it.
 2019-10-08 12:59:52 +08:00
Sebastien Bourdeauducq 4df2c5d1fb sayma: prepare for SYSREF align 
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
 2019-10-08 12:30:47 +08:00
Sebastien Bourdeauducq 03007b896e sayma_amc: sma -> mcx 2019-10-07 20:31:35 +08:00
Sebastien Bourdeauducq 97a0dee3e8 jesd204: remove ibuf_disable 
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
 2019-10-06 22:26:31 +08:00
Sebastien Bourdeauducq f8e4cc37d0 sayma_rtm: reset and detect DACs 2019-10-06 20:15:27 +08:00
Sebastien Bourdeauducq f62dc7e1d4 sayma: refactor JESD DAC channel groups 2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq 1c6c22fde9 sayma_amc: HMC830_REF moved to RTM side 2019-10-06 18:15:37 +08:00
Sebastien Bourdeauducq e6ff44301b sayma_amc: cleanup (v2.0 only) 2019-10-06 18:11:43 +08:00
Sebastien Bourdeauducq e9b81f6e33 remove serwb 
DRTIO is a better solution
 2019-10-06 18:10:23 +08:00
Sebastien Bourdeauducq 7cd02d30b7 sayma_rtm_drtio: replace sayma_rtm 2019-10-06 17:59:53 +08:00
Sebastien Bourdeauducq b3b85135a3 sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase 2019-10-06 17:59:11 +08:00
Sebastien Bourdeauducq 346c985347 sayma_rtm_drtio: use artiq_sayma folder 2019-10-06 17:30:08 +08:00
Sebastien Bourdeauducq 4198033657 sayma_rtm_drtio: cleanup (v2.0 only) 2019-10-06 16:42:34 +08:00
Sebastien Bourdeauducq 5612b31860 sayma_rtm_drtio: add HMC clock chip and DAC control 2019-10-06 16:15:24 +08:00
Sebastien Bourdeauducq a8cf4c2b18 sayma_rtm: hwrev v2.0 by default 2019-10-06 13:25:30 +08:00
Sebastien Bourdeauducq bb5ff46f7d Merge branch 'wrpll' 2019-10-05 10:24:11 +08:00
Sebastien Bourdeauducq 7b95814cf5 sayma_amc: refactor, add SimpleSatellite variant 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 58b7bdcecc sayma_amc: refactor RTM FPGA code 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 96fc4a21e8 sayma_amc: remove dummy FPGA pin assignment testing code 2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq 6aa68e1715 sayma_rtm2: select filtered clock from Si5324 2019-10-04 22:56:16 +08:00
Sebastien Bourdeauducq 6cb0f5de59 sayma_amc: enable DRTIO switching 2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq 0cf8a46bbd sayma_amc2: select filtered clock from Si5324 2019-10-04 21:28:26 +08:00
Robert Jördens f0e87d2e59 grabber: remove unused code 2019-09-20 15:26:12 +02:00
Sebastien Bourdeauducq 991c686d72 kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template 2019-09-11 15:51:53 +08:00
Sebastien Bourdeauducq 7492a59f6d kasli_generic: add SUServo support (#1343) 2019-09-11 11:12:48 +08:00
Sebastien Bourdeauducq 21021beb08 kasli: remove opticlock (moved to kasli_generic) 2019-09-09 15:03:10 +08:00
Sebastien Bourdeauducq cfb5ef5548 kasli_generic: add Novogorny support 2019-09-09 14:54:34 +08:00
Sebastien Bourdeauducq 1fb317778a eem/grabber: allow third EEM to be specified 2019-08-29 18:58:12 +08:00
Sebastien Bourdeauducq 959679d8b7 wrpll: add I2CMasterMachine 2019-08-27 18:02:05 +08:00
Sebastien Bourdeauducq 1fd2322662 wrpll/thls: implement global writeback 2019-08-15 23:16:17 +08:00
Sebastien Bourdeauducq 24082b687e wrpll/filters: clean up and make compatible with thls 2019-08-15 17:58:22 +08:00
Sebastien Bourdeauducq 9331fafab0 wrpll/filters: new code from Weida 2019-08-15 17:24:40 +08:00
Sebastien Bourdeauducq 5c3974c265 wrpll/thls: fix opcode decoding 2019-08-15 17:12:48 +08:00
Sebastien Bourdeauducq 19620948bf wrpll/thls: implement signed numbers 2019-08-15 17:04:17 +08:00
Sebastien Bourdeauducq efc43142a6 wrpll/thls: implement min/max 2019-08-15 16:42:59 +08:00
Sebastien Bourdeauducq 44969b03ad wrpll/thls: rework instruction decoding 2019-08-15 15:55:13 +08:00
Sebastien Bourdeauducq 2776c5b16b wrpll/thls: support mulshift 2019-08-15 15:07:13 +08:00
Sebastien Bourdeauducq f861459ace wrpll: add filter algorithms (WIP) 2019-08-02 13:23:16 +08:00
Sebastien Bourdeauducq 7a5dcbe60e wrpll/thls: support processor start/stop 2019-07-24 18:51:33 +08:00