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aada38f508
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kasli, kc705: remove vivado "keep", cleanup a constraint
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2018-01-23 13:15:26 +00:00 |
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85102e191e
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sayma_rtm: derive clocks automatically
* also don't add false paths unless necessary
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2018-01-23 11:00:55 +00:00 |
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7d1b3f37c9
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sayma_rtm: set CFGBVS/CONFIG_VOLTAGE, compress
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2018-01-23 10:56:42 +00:00 |
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cb0016ceee
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examples/sayma: fix ref_multiplier
SAWG is working, whoohoo!
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2018-01-23 15:26:03 +08:00 |
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cfffd9e13d
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si5324: kasli support
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2018-01-23 13:17:03 +08:00 |
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649deccd9b
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kasli: fix DRTIO satellite QPLL refclksel
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2018-01-23 12:27:19 +08:00 |
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4b4374f76a
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sayma: register_jref for JESD204. Closes #904
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2018-01-23 12:19:15 +08:00 |
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763aefacff
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kasli: fix typo
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2018-01-23 12:10:54 +08:00 |
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c7b148a704
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kasli: when using both GTP clocks, send REFCLK0 to PLL0 and REFCLK1 to PLL1
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2018-01-23 12:08:10 +08:00 |
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d6157514c7
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gtp_7series: flexible QPLL channel selection
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2018-01-23 12:03:09 +08:00 |
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9f87c34a94
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kasli: fix QPLL instantiation
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2018-01-23 10:39:31 +08:00 |
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98a5607634
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gtp_7series: set clock muxes correctly for second QPLL channel
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2018-01-23 10:39:20 +08:00 |
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25fee1a0bb
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gtp_7series: use QPLL second channel
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2018-01-23 10:15:49 +08:00 |
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031d7ff020
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kasli: keep using second QPLL channel for DRTIO satellite
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2018-01-23 10:13:10 +08:00 |
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626075cbc1
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gtp_7series: simplify TX clocking
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2018-01-23 09:49:23 +08:00 |
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472840f16b
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conda: bump migen/misoc
* kasli clock constraint
* vivado false paths
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2018-01-22 20:32:18 +01:00 |
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74b7baa8c5
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urukul example: mmcx clock input
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2018-01-22 20:30:08 +01:00 |
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a86b28def2
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urukul: example additions
* relax timings for faster spi xfers
* continuous readback test to explore spi speed limit
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2018-01-22 20:29:30 +01:00 |
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5a9035b122
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urukul: faster spi clock
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2018-01-22 18:27:40 +00:00 |
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ca1fdaa190
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ad9910: relax timing for faster spi clock
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2018-01-22 18:27:40 +00:00 |
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0d73401365
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conda: bump migen+misoc
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2018-01-23 01:28:10 +08:00 |
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401e57d41c
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gtp_7series: fix nchannels assert
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2018-01-23 01:28:01 +08:00 |
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aa62e91487
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kasli: add DRTIO targets (no firmware)
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2018-01-23 01:27:40 +08:00 |
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296ac35f5d
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sayma_amc: SFP TX disable is active-high
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2018-01-23 00:32:09 +08:00 |
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77192256ea
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kc705: style
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2018-01-23 00:02:35 +08:00 |
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ab7c49d6d0
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sayma_amc: raise error on invalid variant
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2018-01-23 00:02:16 +08:00 |
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c1ac3b66b1
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sayma_rtm: fix 8fe463d4a
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2018-01-23 00:01:45 +08:00 |
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53facfef13
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sayma: build fixes
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2018-01-22 18:33:22 +08:00 |
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25f3feeda8
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refactor targets
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2018-01-22 18:25:10 +08:00 |
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5198c224a2
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sayma,kasli: use new pin names
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2018-01-22 11:51:07 +08:00 |
|
whitequark
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8598e475e9
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artiq_flash: fix a refactoring mistake.
|
2018-01-20 08:30:42 +00:00 |
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c3323f0d57
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hmc830: improve lock failure error report
|
2018-01-20 15:42:53 +08:00 |
|
whitequark
|
115aa0d0d6
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artiq_flash: support load action for Sayma RTM FPGA.
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2018-01-20 07:23:50 +00:00 |
|
whitequark
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94592c7a4c
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artiq_flash: unify flash handling in XC7 and Sayma programmers.
|
2018-01-20 07:23:50 +00:00 |
|
whitequark
|
1ffabac06f
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artiq_flash: use atexit for tempfile cleanup.
|
2018-01-20 07:23:50 +00:00 |
|
whitequark
|
ab9eb56ceb
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setup.py: migen now works on Python 3.6, relax version check.
|
2018-01-20 07:23:50 +00:00 |
|
Florent Kermarrec
|
8fe463d4a0
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sayma_rtm: add UART loopback to easily know if rtm fpga is alive
|
2018-01-20 06:04:34 +01:00 |
|
Florent Kermarrec
|
74ce7319d3
|
sayma: reduce serwb linerate to 625Mbps (make it work on saymas with 1.8v issue, related?)
|
2018-01-20 06:04:18 +01:00 |
|
whitequark
|
f4022ba872
|
remoting: avoid a race condition.
|
2018-01-20 01:30:44 +00:00 |
|
whitequark
|
83278a6edb
|
artiq_flash: fix a refactoring bug.
|
2018-01-20 01:30:44 +00:00 |
|
hartytp
|
37fa3b29da
|
firmware: add register dump on HMC830 lock timeout.
|
2018-01-20 00:19:31 +00:00 |
|
whitequark
|
934bc53cb5
|
artiq_devtool: refactor.
|
2018-01-19 20:35:35 +00:00 |
|
whitequark
|
ebd02c4f43
|
artiq_flash: fix typo.
|
2018-01-19 18:53:49 +00:00 |
|
whitequark
|
1c7cb737ca
|
artiq_flash: refactor.
|
2018-01-19 17:45:49 +00:00 |
|
whitequark
|
bcc39a8c9d
|
artiq_flash: add --dry-run option.
|
2018-01-19 17:45:49 +00:00 |
|
whitequark
|
323c7e66cf
|
artiq_devtool: fix help message.
|
2018-01-19 17:45:49 +00:00 |
|
Florent Kermarrec
|
9eb13aba3c
|
liboard_artiq/hmc830_7043: allow sysref digital/analog delay configuration (will need to be adjusted for jesd subclass1)
|
2018-01-19 17:19:02 +01:00 |
|
Florent Kermarrec
|
d27727968c
|
add artix7 gtp (3gbps), share clock aligner with gth_ultrascale
|
2018-01-19 12:17:54 +01:00 |
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cdbf95d46a
|
kasli: fix permissions
|
2018-01-19 18:31:20 +08:00 |
|
whitequark
|
3c0b164e4d
|
artiq_devtool: update for new board file convention.
Also fix a typo in documentation.
|
2018-01-19 09:43:03 +00:00 |
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