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174c4be218
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phaser: false paths sys<->{jesd,phy.tx}
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2016-11-21 09:57:33 +01:00 |
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b714137f76
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phaser: 150 MHz rtio/jesd clock
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2016-11-19 13:16:30 +01:00 |
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2e482505c6
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phaser: fix DDS dummy cfg
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2016-11-13 17:08:59 +01:00 |
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aedb6747f2
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Merge branch 'master' into phaser
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600).
doc: clarify kernel_invariant doc (fixes #609).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
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2016-11-13 16:54:28 +01:00 |
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99ad9b5917
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add has_dds, use config flags
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2016-11-08 23:33:03 +08:00 |
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d158c69be0
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phaser: fix frequency comment
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2016-11-05 16:54:23 +01:00 |
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2392113bb6
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kc705: use misoc clock for false path
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2016-10-30 11:16:04 +08:00 |
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c656a53532
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kc705: clean up clock constraints
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2016-10-29 21:28:01 +08:00 |
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ed4d57c638
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use new Migen signal attribute API
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2016-10-29 21:19:58 +08:00 |
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2a1e529dcf
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phaser: DDS config dummies
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2016-10-28 01:58:08 +02:00 |
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c428800caf
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phaser: spi, sma_gpio: 2.5 V
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2016-10-27 15:53:49 +02:00 |
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Florent Kermarrec
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0259c80015
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phaser/kc705: remove transceiver initialization workaround
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2016-10-14 19:06:43 +02:00 |
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b41b9de905
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phaser: tag jesd as clock net
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2016-10-14 10:46:33 +02:00 |
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4ea3dea217
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phaser: broad spectrum antibiotics with xilinx false paths
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2016-10-14 10:22:03 +02:00 |
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e400f8d672
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phaser: add two more registers before jesd
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2016-10-14 09:54:56 +02:00 |
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3c9c42c779
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phaser: drive rtio from jesd-bufg
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2016-10-14 02:26:19 +02:00 |
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808874a523
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phaser: drive cd_jesd with BUFG
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2016-10-14 01:57:48 +02:00 |
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342d6d756e
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phaser: bypass gtx phalign
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2016-10-14 00:59:53 +02:00 |
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89150c9817
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phaser: 10G line rate
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2016-10-14 00:53:38 +02:00 |
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42c6658ffe
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phaser: add some more blinking leds
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2016-10-13 15:21:27 +02:00 |
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6a456bd7d4
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phaser: feed correct sink (crucial)
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2016-10-13 15:17:38 +02:00 |
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c8e45ae3f6
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phaser: cleanup jesd phy instantiation a bit
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2016-10-13 14:43:24 +02:00 |
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78a41eec8f
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phaser: kc705: syntax
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2016-10-13 12:38:32 +02:00 |
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Florent Kermarrec
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af0e8582a2
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phaser: use new jesd clocking
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2016-10-13 11:51:06 +02:00 |
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1117fe191b
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phaser: support core stpl
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2016-10-12 12:03:29 +02:00 |
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f515c11f26
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phaser: fix refclk period spec
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2016-10-11 20:13:34 +02:00 |
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bae5b73155
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phaser: comment out stpl test
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2016-10-11 19:50:19 +02:00 |
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2b1cca2e7e
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phaser: stpl
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2016-10-11 19:29:27 +02:00 |
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18d18b6685
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phaser: add sync ttl input for monitoring
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2016-10-10 17:13:23 +02:00 |
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Florent Kermarrec
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c08caae171
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phaser: use qpll
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2016-10-10 17:05:42 +02:00 |
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9b860b26e8
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phaser: fix rtio pll inputs
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2016-10-07 13:00:42 +02:00 |
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09434ec054
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phaser: also adapt rtio_crg
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2016-10-07 12:44:22 +02:00 |
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Florent Kermarrec
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b02a7234f6
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phaser: use 125MHz refclk for jesd
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2016-10-07 08:59:34 +02:00 |
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1193ba4bf4
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ad9154: merge csr spaces
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2016-10-06 16:21:15 +02:00 |
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4d87f0e9e0
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phaser: instantiate jesd204b core, wire up
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2016-10-06 14:44:22 +02:00 |
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4a0eaf0f95
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phaser: add jesd204b rtio dds
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
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2016-10-05 16:17:50 +02:00 |
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8280e72e90
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gateware: use new misoc CSR mapping API
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2016-09-24 20:48:37 +08:00 |
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2bb90a4449
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pipistrello: shrink a few more fifos
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2016-09-21 02:29:05 +02:00 |
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454b48df97
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pipistrello: shrink fifos a bit more to relax pnr
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2016-07-23 12:55:49 +02:00 |
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8cb29fcb3b
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targets/kc705: redefine user SMAs as 3.3V IO. Closes #502
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2016-07-07 14:53:01 +08:00 |
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dhslichter
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141edb521a
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qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
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2016-05-19 10:42:03 +08:00 |
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9707981c07
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targets/kc705: fix default -H option
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2016-04-30 00:30:24 +08:00 |
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dhslichter
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f395a630e0
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Updated qc2 pinouts for SPI and 2x DDS bus, update docs
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2016-04-13 18:38:34 +08:00 |
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ed1c368e73
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gateware: name targets consistently. Closes #290
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2016-04-05 16:07:29 +08:00 |
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8f54a1e619
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pipistrello: sys_clk 83 -> 75 MHz
This should close #341 once migen generates stable output.
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2016-03-21 13:47:32 +01:00 |
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0e1f75ec49
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targets/kc705/qc2: hook up HPC backplane
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2016-03-16 16:19:56 +08:00 |
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f0b0b1bac7
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support for multiple DDS buses (untested)
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2016-03-09 17:12:50 +08:00 |
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f33baf339f
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pipistrello: drop ttls on pmod, add leds back in
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2016-03-08 23:34:51 +01:00 |
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f39208c95a
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pipistrello: try with fewer leds/pmod ttl
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2016-03-08 22:10:47 +01:00 |
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0d431cb019
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pipistrello: make pmod extension header, cleanup
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2016-03-08 17:07:44 +01:00 |
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