mwojcik
1160676fd6
zc706: changed io standard for si5324 on nist backplates
2021-09-15 11:19:43 +02:00
mwojcik
176e370872
kasli_soc satellite: fixed rust config
...
si5324: fixed double mut borrow in soft reset
2021-09-13 15:36:47 +02:00
mwojcik
9c09216281
updated gateware for not yet published migen-axi changes
2021-09-13 15:06:34 +02:00
mwojcik
d3152f3d24
changed auxctrl tx/rx memory to axi2csr_sram
2021-09-10 15:25:05 +02:00
mwojcik
9c14694fc4
added rtioclockmultiplier where applicable
...
(nist variants don't compile for other reasons now)
2021-09-07 15:22:01 +02:00
mwojcik
1bddad6ff2
kasli_soc: fixes to make satellite variant work
2021-09-07 14:51:46 +02:00
mwojcik
76929d2aa1
zc706:
...
* broke down platforms (refactor),
* added nist master/sat variants
* master doesn't build yet, satellite only simple variant
2021-09-06 14:30:09 +02:00
mwojcik
20681a13c4
gateware: fixed cfg keys - case consistent w/ code
2021-09-06 10:57:42 +02:00
mwojcik
9022064cf1
added siphaser to zc706 satellite, small fixes
2021-09-06 09:06:16 +02:00
mwojcik
b678408105
rustc_cfg is case sensitive. Si5324 was not achnowledged.
2021-09-03 14:58:17 +02:00
mwojcik
0c259d9833
kasli_soc: satellite brought to the same level as zc706
2021-09-03 11:05:41 +02:00
mwojcik
37e8b576b1
satellite:
...
* fixing repeaters that can't exist on zc706
* fixing various warnings
* fixed timer and i2c references
2021-08-31 15:25:56 +02:00
mwojcik
ff7ba56d26
forgot to remove a debug print
2021-08-26 12:54:19 +02:00
mwojcik
b585eaaa37
zc706: added memory iface generator
2021-08-24 13:51:38 +02:00
mwojcik
1358c8bfe9
zc706 gateware: base class for drtio is SoCCore
2021-08-24 12:01:04 +02:00
mwojcik
b2d9003d9f
drtioaucontroller: made two decoders
2021-08-20 15:13:56 +02:00
mwojcik
e43684a3ed
moved AXI SRAM to migen-axi
2021-08-18 12:36:17 +02:00
mwojcik
7b868e1c9d
few fixes, typos and missed unnecessary statements
2021-08-17 13:16:02 +02:00
mwojcik
61f81cec47
sram: redesigned write FSM. removed unused signals
2021-08-17 11:10:08 +02:00
mwojcik
3e1d14ff38
replaced increment logic with ready Incr module
2021-08-16 15:33:50 +02:00
mwojcik
67ed7fae78
sram: or operator in wrong place for wrapped burst
2021-08-16 12:05:23 +02:00
mwojcik
f015d6732b
sram: support for different burst settings on read
2021-08-16 11:51:50 +02:00
mwojcik
b6dd5bea68
sram: fixed wrong assumptions on some signals
2021-08-13 14:58:18 +02:00
mwojcik
bfe0c34f57
sram: rewrote read fsm for sram
2021-08-13 14:14:43 +02:00
mwojcik
39509f01d6
aux_controller: sram ported to axi, first attempt
2021-08-13 13:06:10 +02:00
mwojcik
066987bf07
aux_controller: started porting from wb to axi
2021-08-11 14:34:44 +02:00
mwojcik
7ff59f57a9
gateware: updated gtx interface
2021-08-10 15:11:21 +02:00
mwojcik
118893c0b2
disabled adding axi slave/mem
...
drtioauxcontroller uses AXI rather than Wishbone
still won't compile - unresolved clock domain error
2021-08-06 15:25:59 +02:00
mwojcik
ae86bbb76e
zc706 gateware fixes:
...
replaced crg cd_sys.clk with ps7.cd_sys.clk
restored gpio
removed mentions of i2c
user_sma_clock consumed by _RTIOCRG already
2021-08-06 13:31:16 +02:00
mwojcik
d68cf7dd49
gateware: replaced wb slave w/ axi (diff soccore)
2021-08-06 11:05:49 +02:00
mwojcik
f9860a61b7
sys_clk_freq is actually 125mhz
2021-08-06 10:39:37 +02:00
mwojcik
d1705113aa
kasli: gtx transcvr expects separate tx/rx pads
2021-08-06 10:05:45 +02:00
mwojcik
97dfa07bdb
determined probable sys_clk_freq for GTX transcvr
2021-08-06 10:05:04 +02:00
mwojcik
ecc8a0ccc0
kasli-soc: qpll is not part of this board, removed mentions
2021-08-04 16:44:08 +02:00
mwojcik
b95692548e
Merge branch 'master' into drtio_port
2021-08-04 09:38:08 +02:00
Sebastien Bourdeauducq
18e05c91e1
zc706: si5324 is not needed for standalone target
2021-08-04 09:14:19 +08:00
mwojcik
e3d3cb2311
si5324: bring on par with mainline ARTIQ ( #132 )
...
si5324 driver in runtime should be now equal in function to the one in artiq.
kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.
Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
mwojcik
6a9729bede
Merge branch 'master' into drtio_port
2021-08-03 09:56:14 +02:00
mwojcik
b2dd68bd92
removed unnecessary and wrong add_drtio
2021-08-03 09:52:50 +02:00
mwojcik
cafbe97e47
zc706: added targets to default.nix, fixed wrong base cls
2021-07-30 15:14:40 +02:00
mwojcik
3ba7fe1e6b
kasli_soc uses gtx transceiver instead of gtp
2021-07-30 12:52:58 +02:00
Sebastien Bourdeauducq
8128dc0b56
Revert "kasli-soc: work around I2C breakage ( #130 )"
...
This reverts commit f1fd55dee5
.
2021-07-30 16:55:06 +08:00
mwojcik
0ce86317c9
zc706: added rough master/satellite drtio support
2021-07-29 15:38:23 +02:00
mwojcik
248530faf1
gateware: kasli_soc - first attempt at drtio
2021-07-29 13:41:02 +02:00
Sebastien Bourdeauducq
852123b42a
kasli-soc: add RTIO LEDs
2021-05-30 20:40:53 +08:00
Sebastien Bourdeauducq
f1fd55dee5
kasli-soc: work around I2C breakage ( #130 )
2021-05-29 17:13:41 +08:00
Sebastien Bourdeauducq
506c741238
support absence of gateware RTIO clock selection mux
2021-02-15 21:41:30 +08:00
Sebastien Bourdeauducq
8815f76114
kasli_soc: fix has_grabber
2021-02-15 21:41:02 +08:00
Sebastien Bourdeauducq
ef18fa4c6d
kasli_soc: add RTIO log channel
2021-02-15 19:56:59 +08:00
Sebastien Bourdeauducq
faf9714e10
add demo build for Kasli-SoC
2021-02-15 19:52:13 +08:00