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zc706: added memory iface generator

drtio_port
mwojcik 2021-08-24 13:51:38 +02:00
parent 1358c8bfe9
commit b585eaaa37
1 changed files with 11 additions and 0 deletions
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11
src/gateware/zc706.py
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@ -530,6 +530,11 @@ def write_csr_file(soc, filename):
f.write(cpu_interface.get_csr_rust(
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
def write_mem_file(soc, filename):
with open(filename, "w") as f:
f.write(cpu_interface.get_mem_rust(
soc.get_memory_regions(), soc.get_memory_groups(), None))
def write_rustc_cfg_file(soc, filename):
with open(filename, "w") as f:
@ -545,6 +550,8 @@ def main():
description="ARTIQ port to the ZC706 Zynq development kit")
parser.add_argument("-r", default=None,
help="build Rust interface into the specified file")
parser.add_argument("-m", default=None,
help="build Rust memory interface into the specified file")
parser.add_argument("-c", default=None,
help="build Rust compiler configuration into the specified file")
parser.add_argument("-g", default=None,
@ -567,8 +574,12 @@ def main():
soc = cls(acpki=acpki)
soc.finalize()
print(soc.get_memory_regions())
if args.r is not None:
write_csr_file(soc, args.r)
if args.m is not None:
write_mem_file(soc, args.m)
if args.c is not None:
write_rustc_cfg_file(soc, args.c)
if args.g is not None: