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sys_clk_freq is actually 125mhz

drtio_port
mwojcik 2021-08-06 10:39:37 +02:00
parent d1705113aa
commit f9860a61b7
2 changed files with 5 additions and 11 deletions
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8
src/gateware/kasli_soc.py
View File

@ -187,9 +187,7 @@ class GenericMaster(SoCCore):
mem_map.update(SoCCore.mem_map)
def __init__(self, description, acpki=False):
sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL?
# not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly
# necessary for GTX transceiver
sys_clk_freq = 125e6
rtio_clk_freq = 125e6 # should this be pulled from description? rtio freq isnt set
self.acpki = acpki
@ -331,9 +329,7 @@ class GenericSatellite(SoCCore):
mem_map.update(SoCCore.mem_map)
def __init__(self, description, acpki=False):
sys_clk_freq = 800e6 # this is not set within SoCCore anymore, but rather - by SZL?
# not sure if it should be ArmPLL/CPU/IoPLL freq - they differ slightly
# necessary for GTX transceiver
sys_clk_freq = 125e6
rtio_clk_freq = 125e6 # same thing as with master - pulled from desc?
# will probably be replaced with rtio_config key as per #1735

8
src/gateware/zc706.py
View File

@ -269,9 +269,8 @@ class Master(ZC706):
def __init__(self, **kwargs):
ZC706.__init__(self, **kwargs)
sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL
# again not sure if correct value
sys_clk_freq = 125e6
platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1)
@ -373,8 +372,7 @@ class Satellite(ZC706):
def __init__(self, **kwargs):
ZC706.__init__(self, **kwargs)
sys_clk_freq = 800e6 # same as in Kasli-SoC - CPU freq set by SZL
# again not sure if correct value
sys_clk_freq = 125e6
platform = self.platform