forked from M-Labs/artiq-zynq
aux_controller: sram ported to axi, first attempt
parent
066987bf07
commit
39509f01d6
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@ -9,18 +9,204 @@ from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
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max_packet = 1024
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OUT_BURST_LEN = 10
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IN_BURST_LEN = 4
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=False, init=None, bus=None):
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# SRAM initialisation
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if bus is None:
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bus = axi.Interface()
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self.bus = bus
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bus_data_width = len(self.bus.r.data)
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bus_addr_width = len(self.bus.ar.addr)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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# memory
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
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self.specials += self.mem, port
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###
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# probably will get removed
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self.addr_base = CSRStorage(32)
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self.trig_count = CSRStatus(32)
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self.write_count = CSRStatus(32)
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self.trigger_stb = Signal()
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# Dout : Data received from CPU, output by SRAM <- port.dat_r
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# Din : Data driven into SRAM, written into CPU <- port.dat_w
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# When stb assert, index shows word being read/written, dout/din holds <- will be removed
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# data
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#
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# Cycle:
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# trigger_stb pulsed at start
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# Then out_burst_len words are strobed out of dout
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# Then, when din_ready is high, in_burst_len words are strobed in to din
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self.dout_stb = Signal() # there's no strobe signal for SRAM
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self.din_stb = Signal()
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self.dout_index = Signal(bus_addr_width) # is this legal?
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self.din_index = Signal(bus_addr_width)
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self.din_ready = Signal()
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self.dout = Signal(64)
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self.din = Signal(64)
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# probably not correct here
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self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
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ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
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### Read
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self.comb += [
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ar.addr.eq(port.adr), # shouldn't it be the other way around?
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port.dat_r.eq(r.data),
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r.ready.eq(1),
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ar.burst.eq(axi.Burst.incr.value),
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ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
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ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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ar.cache.eq(0xf),
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]
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# read control
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self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
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read_fsm.act("IDLE",
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If(self.trigger_stb,
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ")
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).Else(
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NextState("READ_START")
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)
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)
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)
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read_fsm.act("READ_START",
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ar.valid.eq(1),
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If(ar.ready,
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NextState("READ"),
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)
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)
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read_fsm.act("READ",
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ar.valid.eq(0),
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If(r.last & r.valid,
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NextState("IDLE")
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)
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)
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self.sync += [
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If(read_fsm.ongoing("IDLE"),
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self.dout_index.eq(0)
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).Else(If(r.valid & read_fsm.ongoing("READ"),
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self.dout_index.eq(self.dout_index+1),
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port.adr.eq(port.adr + self.dout_index) # update address in the port
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)
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)
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]
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# possibly unnecessary too
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self.comb += self.dout_stb.eq(r.valid & r.ready)
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### Write
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self.comb += [
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w.data.eq(port.dat_w),
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aw.addr.eq(port.addr), # shouldn't it be the other way around?
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w.strb.eq(0xff),
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aw.burst.eq(axi.Burst.incr.value),
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aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
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aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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aw.cache.eq(0xf),
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b.ready.eq(1),
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]
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.valid.eq(0),
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aw.valid.eq(0),
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If(self.trigger_stb,
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aw.valid.eq(1),
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If(aw.ready, # assumes aw.ready is not randomly deasserted
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NextState("DATA_WAIT")
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).Else(
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NextState("AW_READY_WAIT")
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)
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)
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)
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write_fsm.act("AW_READY_WAIT",
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aw.valid.eq(1),
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If(aw.ready,
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NextState("DATA_WAIT"),
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)
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)
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write_fsm.act("DATA_WAIT",
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aw.valid.eq(0),
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If(self.din_ready, # probably unnecessary?
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w.valid.eq(1),
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NextState("WRITE")
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)
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)
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write_fsm.act("WRITE",
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w.valid.eq(1),
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If(w.ready & w.last,
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NextState("IDLE")
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)
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)
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# refer to port.we instead
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self.sync += If(w.ready & w.valid, port.we.eq(1))
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self.sync += [
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If(write_fsm.ongoing("IDLE"),
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self.din_index.eq(0) # replace with address?
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), # but need to synchronise the address too
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If(w.ready & w.valid, self.din_index.eq(self.din_index+1), port.adr.eq(port.addr+self.din_index))
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]
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self.comb += [
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w.last.eq(0),
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If(self.din_index==aw.len, w.last.eq(1))
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]
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# check if necessary
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self.comb += self.din_stb.eq(w.valid & w.ready)
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# # generate write enable signal
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# if not read_only:
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# # replace with? stb -> w.strb we->w.ready? sel[i]-> r.valid
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# self.comb += [port.we[i].eq(self.bus.cyc & self.bus.w.strb & self.bus.w.ready & self.bus.r.valid)
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# for i in range(4)]
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# # address and data
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# self.comb += [
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# self.bus.r.ready.eq(self.bus.r.valid), # AXI handshake?
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# port.adr.eq(self.bus.ar.addr[:len(port.adr)]),
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# self.bus.r.data.eq(port.dat_r)
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# ]
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# if not read_only:
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# self.comb += port.dat_w.eq(self.bus.w.data),
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# # generate ack
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# self.sync += [
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# self.bus.ack.eq(0),
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# If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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# ]
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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class DRTIOAuxController(Module):
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def __init__(self, link_layer):
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self.bus = axi.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.data_width))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.data_width))
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
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# probably will need to make axi.SDRAM based on wb code
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tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.bus.data_width)//8)
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# probably will need to make axi.SRAM based on wb code
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tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.w.data)//8)
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decoder = axi.AddressDecoder(self.bus,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
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