stevefan1999
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

kasli-soc: qpll is not part of this board, removed mentions

drtio_port
mwojcik 2021-08-04 16:44:08 +02:00
parent e17b398483
commit ecc8a0ccc0
1 changed files with 0 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/gateware/kasli_soc.py
View File

@ -213,11 +213,6 @@ class GenericMaster(SoCCore):
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
# todo figure out cdr lk clean
# self.sync += self.disable_cdr_clk_ibuf.eq(
# ~self.drtio_transceiver.stable_clkin.storage)
# ====end drtio for now
self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.rtio_crg = RTIOCRG(self.platform)
@ -243,8 +238,6 @@ class GenericMaster(SoCCore):
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
# lifted from MasterBase
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
@ -278,8 +271,6 @@ class GenericMaster(SoCCore):
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
# lift end
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
self.csr_devices.append("rtio_core")
@ -352,11 +343,6 @@ class GenericSatellite(SoCCore):
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
# same here - figure out the relations
# self.sync += disable_cdr_clk_ibuf.eq(
# ~self.drtio_transceiver.stable_clkin.storage)
sfp_channels = self.drtio_transceiver.channels
self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.rtio_crg = RTIOCRG(self.platform)