forked from M-Labs/artiq-zynq
moved AXI SRAM to migen-axi
parent
7b868e1c9d
commit
e43684a3ed
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@ -1,163 +1,13 @@
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"""Auxiliary controller, common to satellite and master"""
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from operator import attrgetter
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from migen import *
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from migen_axi.interconnect import axi
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from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from migen_axi.interconnect.sram import SRAM
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from migen_axi.interconnect import axi
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max_packet = 1024
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OUT_BURST_LEN = 10
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IN_BURST_LEN = 4
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class SRAM(Module):
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def __init__(self, mem_or_size, read_only=False, init=None, bus=None):
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# SRAM initialisation
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if bus is None:
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bus = axi.Interface()
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self.bus = bus
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bus_data_width = len(self.bus.r.data)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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# memory
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
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self.specials += self.mem, port
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###
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ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
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# Dout : Data received from CPU, output by SRAM <- port.dat_r
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# Din : Data driven into SRAM, written into CPU <- port.dat_w
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self.dout_index = Signal.like(ar.len)
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self.r_addr_incr = axi.Incr(ar)
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self.w_addr_incr = axi.Incr(aw)
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### Read
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self.comb += [
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r.data.eq(port.dat_r),
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port.adr.eq(self.r_addr_incr.addr)
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]
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# read control
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self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
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read_fsm.act("IDLE",
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If(ar.valid,
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port.adr.eq(self.r_addr_incr.addr),
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ar.ready.eq(1),
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NextState("READ_START"),
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)
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)
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read_fsm.act("READ_START",
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r.resp.eq(axi.Response.okay.value),
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r.valid.eq(1),
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If(r.ready,
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NextState("READ"))
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)
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read_fsm.act("READ",
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If(r.last & r.ready, # that's a smart way of skipping "LAST" state
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NextState("IDLE")
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)
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)
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self.sync += [
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If(read_fsm.ongoing("IDLE"),
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self.dout_index.eq(0),
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r.valid.eq(0), # shall it be reset too on IDLE?
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ar.ready.eq(0),
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r.last.eq(0)
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).Else(If(r.ready & read_fsm.ongoing("READ"),
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self.dout_index.eq(self.dout_index+1),
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If(self.dout_index==ar.len, r.last.eq(1)) # and update last
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)
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)
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]
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### Write
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if not read_only:
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self.comb += [
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port.dat_w.eq(w.data),
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port.adr.eq(self.w_addr_incr.addr),
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]
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.ready.eq(0),
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aw.ready.eq(0),
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b.valid.eq(0),
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If(aw.valid,
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NextState("AW_VALID_WAIT")
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)
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)
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write_fsm.act("AW_VALID_WAIT", # wait for data
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aw.ready.eq(1),
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If(w.valid,
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NextState("WRITE"),
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)
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)
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# write_fsm.act("DATA_WAIT",
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# aw.valid.eq(0),
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# If(self.din_ready,
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# w.valid.eq(1),
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# NextState("WRITE")
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# )
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# )
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write_fsm.act("WRITE",
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w.ready.eq(1),
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If(w.ready & w.last,
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NextState("WRITE_RESP")
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)
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)
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write_fsm.act("WRITE_RESP",
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port.we.eq(0),
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b.resp.eq(axi.Response.okay.value),
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b.valid.eq(1),
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If(b.ready,
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NextState("IDLE")
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)
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)
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self.sync += If(w.ready & w.valid, port.we.eq(1))
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# self.sync += [
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# If(write_fsm.ongoing("IDLE"),
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# self.din_index.eq(0)
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# ), # but need to synchronise the address too)
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# ]
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# # generate write enable signal
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# if not read_only:
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# # replace with? stb -> w.strb we->w.ready? sel[i]-> r.valid
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# self.comb += [port.we[i].eq(self.bus.cyc & self.bus.w.strb & self.bus.w.ready & self.bus.r.valid)
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# for i in range(4)]
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# # address and data
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# self.comb += [
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# self.bus.r.ready.eq(self.bus.r.valid), # AXI handshake?
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# port.adr.eq(self.bus.ar.addr[:len(port.adr)]),
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# self.bus.r.data.eq(port.dat_r)
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# ]
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# if not read_only:
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# self.comb += port.dat_w.eq(self.bus.w.data),
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# # generate ack
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# self.sync += [
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# self.bus.ack.eq(0),
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# If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
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# ]
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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