kasli_soc: satellite brought to the same level as zc706

src/gateware/kasli_soc.py

@@ -179,10 +179,10 @@ class GenericStandalone(SoCCore):
         
 class GenericMaster(SoCCore):
     mem_map = {
-        "cri_con":       0x10000000,
-        "rtio":          0x20000000,
-        "rtio_dma":      0x30000000,
-        "drtioaux":      0x50000000
+        # "cri_con":       0x10000000,
+        # "rtio":          0x20000000,
+        # "rtio_dma":      0x30000000,
+        "drtioaux":      0x40000000
     }
     mem_map.update(SoCCore.mem_map)
 
@@ -313,7 +313,7 @@ class GenericMaster(SoCCore):
 
 class GenericSatellite(SoCCore):
     mem_map = {
-        "drtioaux":      0x50000000
+        "drtioaux":      0x40000000
     }
     mem_map.update(SoCCore.mem_map)
 
@@ -479,6 +479,11 @@ class GenericSatellite(SoCCore):
                     self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
      
 
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
 
 def write_csr_file(soc, filename):
     with open(filename, "w") as f:
@@ -502,6 +507,8 @@ def main():
         help="build Rust interface into the specified file")
     parser.add_argument("-c", default=None,
         help="build Rust compiler configuration into the specified file")
+    parser.add_argument("-m", default=None,
+        help="build Rust memory interface into the specified file")
     parser.add_argument("-g", default=None,
         help="build gateware into the specified directory")
     parser.add_argument("--acpki", default=False, action="store_true",
@@ -528,6 +535,8 @@ def main():
 
     if args.r is not None:
         write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
     if args.c is not None:
         write_rustc_cfg_file(soc, args.c)
     if args.g is not None: