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few fixes, typos and missed unnecessary statements

drtio_port
mwojcik 2021-08-17 13:16:02 +02:00
parent 61f81cec47
commit 7b868e1c9d
2 changed files with 15 additions and 16 deletions
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18
src/gateware/aux_controller.py
View File

@ -1,5 +1,7 @@
"""Auxiliary controller, common to satellite and master"""
from operator import attrgetter
from migen import *
from migen.fhdl.simplify import FullMemoryWE
@ -88,7 +90,7 @@ class SRAM(Module):
if not read_only:
self.comb += [
port.dat_w.eq(w.data),
port.addr.eq(self.w_addr_incr.addr),
port.adr.eq(self.w_addr_incr.addr),
]
self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
@ -131,11 +133,11 @@ class SRAM(Module):
self.sync += If(w.ready & w.valid, port.we.eq(1))
self.sync += [
If(write_fsm.ongoing("IDLE"),
self.din_index.eq(0)
), # but need to synchronise the address too)
]
# self.sync += [
# If(write_fsm.ongoing("IDLE"),
# self.din_index.eq(0)
# ), # but need to synchronise the address too)
# ]
# # generate write enable signal
@ -159,7 +161,7 @@ class SRAM(Module):
# TODO: FullMemoryWE should be applied by migen.build
@FullMemoryWE()
class DRTIOAuxController(Module):
class DRTIOAuxControllerAxi(Module):
def __init__(self, link_layer):
self.bus = axi.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
@ -168,7 +170,7 @@ class DRTIOAuxController(Module):
# probably will need to make axi.SRAM based on wb code
tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.w.data)//8)
wsb = log2_int(len(self.bus.w.data)//8)
decoder = axi.AddressDecoder(self.bus,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],

13
src/gateware/zc706.py
View File

@ -24,6 +24,7 @@ from artiq.gateware.drtio import *
import dma
import analyzer
import acpki
import aux_controller
class RTIOCRG(Module, AutoCSR):
@ -308,14 +309,12 @@ class Master(ZC706):
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
# self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
# currently removed - DRTIOAuxController works with Wishbone
# while the board supports AXI
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
@ -410,14 +409,12 @@ class Satellite(ZC706):
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
# self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
# currently removed - DRTIOAuxController works with Wishbone
# while the board supports AXI
self.register_mem(memory_name, memory_address, 0x800, coreaux.bus)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)