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kasli_soc satellite: fixed rust config 

si5324: fixed double mut borrow in soft reset
drtio_port
mwojcik 2021-09-13 15:36:47 +02:00
parent 9c09216281
commit 176e370872
2 changed files with 6 additions and 6 deletions
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9
src/gateware/kasli_soc.py
View File

@ -361,9 +361,8 @@ class GenericSatellite(SoCCore):
self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
# put range(1) to make it work while axi doesn't support anything but P2P
data_pads = [platform.request("sfp", i) for i in range(1)]
data_pads = [platform.request("sfp", i) for i in range(4)]
self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx?
@ -431,8 +430,8 @@ class GenericSatellite(SoCCore):
# and registered in PS interface
# manually, because software refers to rx/tx by halves of entire memory block, not names
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
self.config["has_drtio"] = None
self.config["has_drtio_routing"] = None
self.rustc_cfg["has_drtio"] = None
self.rustc_cfg["has_drtio_routing"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)

3
src/libboard_artiq/src/si5324.rs
View File

@ -148,7 +148,8 @@ fn ident(i2c: &mut I2c) -> Result<u16> {
#[cfg(si5324_soft_reset)]
fn soft_reset(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
write_no_ack_value(i2c, 136, read(i2c, 136)? | 0x80)?;
let val = read(i2c, 136)?;
write_no_ack_value(i2c, 136, val | 0x80)?;
timer.delay_us(10_000);
Ok(())
}