forked from M-Labs/artiq-zynq
sram: redesigned write FSM. removed unused signals
parent
3e1d14ff38
commit
61f81cec47
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@ -21,7 +21,6 @@ class SRAM(Module):
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bus = axi.Interface()
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self.bus = bus
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bus_data_width = len(self.bus.r.data)
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bus_addr_width = len(self.bus.ar.addr)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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@ -34,21 +33,21 @@ class SRAM(Module):
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###
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# Dout : Data received from CPU, output by SRAM <- port.dat_r
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# Din : Data driven into SRAM, written into CPU <- port.dat_w
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self.dout_index = Signal(bus_addr_width) # is this legal?
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self.din_index = Signal(bus_addr_width)
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self.din_ready = Signal()
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self.dout = Signal(64)
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self.din = Signal(64)
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ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
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# Dout : Data received from CPU, output by SRAM <- port.dat_r
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# Din : Data driven into SRAM, written into CPU <- port.dat_w
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self.dout_index = Signal.like(ar.len)
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self.r_addr_incr = axi.Incr(ar)
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self.w_addr_incr = axi.Incr(aw)
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### Read
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self.comb += r.data.eq(port.dat_r)
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self.comb += [
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r.data.eq(port.dat_r),
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port.adr.eq(self.r_addr_incr.addr)
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]
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# read control
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self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
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@ -60,15 +59,12 @@ class SRAM(Module):
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)
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)
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read_fsm.act("READ_START",
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r.data.eq(port.dat_r),
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r.resp.eq(axi.Response.okay.value),
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r.valid.eq(1),
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If(r.ready,
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r.data.eq(port.dat_r), # that should be always updated, right?
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NextState("READ"))
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)
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read_fsm.act("READ",
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r.data.eq(port.dat_r),
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If(r.last & r.ready, # that's a smart way of skipping "LAST" state
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NextState("IDLE")
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)
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@ -79,73 +75,67 @@ class SRAM(Module):
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self.dout_index.eq(0),
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r.valid.eq(0), # shall it be reset too on IDLE?
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ar.ready.eq(0),
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r.last.eq(0)
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).Else(If(r.ready & read_fsm.ongoing("READ"),
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self.dout_index.eq(self.dout_index+1),
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port.adr.eq(self.r_addr_incr.addr),
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If(self.dout_index==ar.len, r.last.eq(1)) # and update last
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)
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)
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]
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### Write
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self.comb += [
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port.dat_w.eq(w.data),
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port.addr.eq(aw.addr),
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# w.strb.eq(0xff),
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# aw.burst.eq(axi.Burst.incr.value),
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# aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
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# aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
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# aw.cache.eq(0xf),
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# b.ready.eq(1),
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]
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.valid.eq(0),
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aw.valid.eq(0),
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If(self.trigger_stb,
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aw.valid.eq(1),
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If(aw.ready, # assumes aw.ready is not randomly deasserted
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NextState("DATA_WAIT")
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).Else(
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NextState("AW_READY_WAIT")
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if not read_only:
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self.comb += [
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port.dat_w.eq(w.data),
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port.addr.eq(self.w_addr_incr.addr),
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]
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self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
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write_fsm.act("IDLE",
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w.ready.eq(0),
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aw.ready.eq(0),
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b.valid.eq(0),
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If(aw.valid,
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NextState("AW_VALID_WAIT")
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)
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)
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)
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write_fsm.act("AW_READY_WAIT",
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aw.valid.eq(1),
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If(aw.ready,
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NextState("DATA_WAIT"),
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write_fsm.act("AW_VALID_WAIT", # wait for data
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aw.ready.eq(1),
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If(w.valid,
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NextState("WRITE"),
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)
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)
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)
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write_fsm.act("DATA_WAIT",
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aw.valid.eq(0),
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If(self.din_ready, # probably unnecessary?
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w.valid.eq(1),
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NextState("WRITE")
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# write_fsm.act("DATA_WAIT",
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# aw.valid.eq(0),
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# If(self.din_ready,
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# w.valid.eq(1),
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# NextState("WRITE")
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# )
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# )
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write_fsm.act("WRITE",
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w.ready.eq(1),
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If(w.ready & w.last,
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NextState("WRITE_RESP")
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)
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)
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)
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write_fsm.act("WRITE",
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w.valid.eq(1),
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If(w.ready & w.last,
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NextState("IDLE")
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write_fsm.act("WRITE_RESP",
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port.we.eq(0),
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b.resp.eq(axi.Response.okay.value),
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b.valid.eq(1),
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If(b.ready,
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NextState("IDLE")
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)
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)
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)
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# refer to port.we instead
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self.sync += If(w.ready & w.valid, port.we.eq(1))
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self.sync += If(w.ready & w.valid, port.we.eq(1))
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self.sync += [
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If(write_fsm.ongoing("IDLE"),
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self.din_index.eq(0)
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), # but need to synchronise the address too
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If(w.ready & w.valid, self.din_index.eq(self.din_index+1), port.adr.eq(port.addr+self.din_index))
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]
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self.comb += [
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w.last.eq(0),
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If(self.din_index==aw.len, w.last.eq(1))
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]
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self.sync += [
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If(write_fsm.ongoing("IDLE"),
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self.din_index.eq(0)
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), # but need to synchronise the address too)
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]
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# # generate write enable signal
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