 Sebastien Bourdeauducq
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da5208e160
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drtio: add master gateware target
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2016-10-29 17:31:15 +08:00 |
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Sebastien Bourdeauducq
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7c05dccf65
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drtio: add support for 125MHz clock on GTX_1000BASE_BX10
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2016-10-29 17:30:29 +08:00 |
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Sebastien Bourdeauducq
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95def81c03
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drtio: squelch frame signals until link layer ready
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2016-10-29 17:05:30 +08:00 |
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Sebastien Bourdeauducq
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4f6241283c
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drtio: always use NoRetiming on MultiReg inputs
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2016-10-29 16:37:53 +08:00 |
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Sebastien Bourdeauducq
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9bbc6eb0ef
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drtio: more full stack testing
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2016-10-26 22:04:32 +08:00 |
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Sebastien Bourdeauducq
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929a7650a8
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drtio: fixes
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2016-10-26 22:03:44 +08:00 |
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Sebastien Bourdeauducq
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45621934fd
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drtio: forward errors to CSR
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2016-10-26 22:03:05 +08:00 |
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Sebastien Bourdeauducq
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7f8e53aa5c
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drtio: more fixes and tests
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2016-10-26 11:48:47 +08:00 |
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Sebastien Bourdeauducq
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22173b8c70
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drtio: full stack unittest
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2016-10-26 00:35:22 +08:00 |
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Sebastien Bourdeauducq
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f763b519f4
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drtio: fix channel selection
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2016-10-26 00:33:21 +08:00 |
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Sebastien Bourdeauducq
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ad042de954
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drtio: fixes, basic TTL working in simulation
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2016-10-25 12:41:16 +08:00 |
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Sebastien Bourdeauducq
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94e68dbae4
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drtio: test_full_stack (WIP)
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2016-10-24 23:36:33 +08:00 |
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Sebastien Bourdeauducq
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a4e85081aa
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drtio: more simple fixes
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2016-10-24 23:32:49 +08:00 |
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Sebastien Bourdeauducq
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029e0d95b7
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drtio: simple fixes
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2016-10-24 23:10:15 +08:00 |
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Sebastien Bourdeauducq
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c39987b617
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drtio: handle underflow/sequence error CSRs
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2016-10-24 20:46:55 +08:00 |
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Sebastien Bourdeauducq
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7dd6eb2f5e
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drtio: add RT write controller
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2016-10-24 19:50:13 +08:00 |
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Sebastien Bourdeauducq
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83bec06226
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drtio: fifo level -> fifo space
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2016-10-24 15:59:12 +08:00 |
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Sebastien Bourdeauducq
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aa8e211735
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drtio/rt_packets: fix
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2016-10-22 13:03:35 +08:00 |
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Sebastien Bourdeauducq
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449d1c4dc6
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rtio: export CDC modules
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2016-10-22 13:03:10 +08:00 |
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Sebastien Bourdeauducq
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67c19ab178
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drtio: RTPacketMaster RX, untested
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2016-10-22 01:04:14 +08:00 |
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Sebastien Bourdeauducq
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3b4a40401a
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drtio: RTPacketMaster TX (WIP)
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2016-10-21 22:46:14 +08:00 |
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Sebastien Bourdeauducq
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1e313afe64
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drtio: CrossDomainNotification
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2016-10-21 22:45:45 +08:00 |
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Sebastien Bourdeauducq
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c71c4c89e0
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drtio: change data direction in _CrossDomainRequest
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2016-10-21 22:44:47 +08:00 |
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Sebastien Bourdeauducq
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6a88229e6a
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drtio: CrossDomainRequest
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2016-10-20 23:37:59 +08:00 |
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Sebastien Bourdeauducq
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9790c5d9ed
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drtio/iot: FIFO level
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2016-10-19 18:04:03 +08:00 |
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Sebastien Bourdeauducq
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71480c4d15
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drtio: fix mmcm_mult
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2016-10-18 17:28:03 +08:00 |
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Sebastien Bourdeauducq
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e7dbed3b02
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gateware: KC705 satellite target
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2016-10-17 19:23:45 +08:00 |
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Sebastien Bourdeauducq
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9752ffe3d1
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drtio: various fixes
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2016-10-17 19:23:08 +08:00 |
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Sebastien Bourdeauducq
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cce29e8b83
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gateware/spi: fix import
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2016-10-17 14:47:19 +08:00 |
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Sebastien Bourdeauducq
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d3b274fc4d
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drtio: synchronizer MMCM
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2016-10-16 17:40:58 +08:00 |
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Sebastien Bourdeauducq
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03d3a85e75
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drtio: RX clock alignment and ready
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2016-10-15 18:36:27 +08:00 |
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Sebastien Bourdeauducq
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08e4aa3e3f
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drtio: GTX WIP
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2016-10-14 00:36:13 +08:00 |
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Sebastien Bourdeauducq
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c548a65ec3
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drtio: clock domains
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2016-10-14 00:34:59 +08:00 |
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Sebastien Bourdeauducq
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018f6d1b52
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drtio: implement basic IOT
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2016-10-11 17:59:22 +08:00 |
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Sebastien Bourdeauducq
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a40b39e9a2
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drtio: structure
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2016-10-10 23:12:12 +08:00 |
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Sebastien Bourdeauducq
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87ec333f55
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drtio: implement basic writes, errors, fifo levels on satellite
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2016-10-10 00:13:41 +08:00 |
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Sebastien Bourdeauducq
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23b3302200
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drtio: implement TSC load in satellite
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2016-10-07 19:30:53 +08:00 |
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Sebastien Bourdeauducq
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43caffc168
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drtio: self-checking echo test
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2016-10-07 17:31:51 +08:00 |
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Sebastien Bourdeauducq
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0574e882d2
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drtio: basic RT packet echo test
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2016-10-07 15:36:32 +08:00 |
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Sebastien Bourdeauducq
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cb0d1549c6
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drtio: add rt_packets TX datapath, fixes
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2016-10-07 15:35:29 +08:00 |
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Sebastien Bourdeauducq
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76bac21d14
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drtio: RT RX datapath, untested
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2016-10-06 18:51:20 +08:00 |
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Sebastien Bourdeauducq
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1e0c6d6d5d
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drtio: monitor received link_init
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2016-09-30 11:25:06 +08:00 |
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Sebastien Bourdeauducq
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cefb9e1405
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drtio: add full link layer
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2016-09-27 21:41:57 +08:00 |
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Sebastien Bourdeauducq
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08772f7a71
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drtio: add RX ready signaling
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2016-09-27 19:02:54 +08:00 |
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Sebastien Bourdeauducq
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95d7cba34a
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drtio: fixes, add aux packet test
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2016-09-27 12:46:01 +08:00 |
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Sebastien Bourdeauducq
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e59142e344
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drtio: use additive scrambler reset by link init
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2016-09-27 11:38:05 +08:00 |
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Sebastien Bourdeauducq
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8a92c2c7e5
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drtio: add RX link layer, fixes, simple loopback demo
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2016-09-27 11:23:29 +08:00 |
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Sebastien Bourdeauducq
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4e47decdbc
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drtio: add scrambler/descrambler and test
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2016-09-26 14:14:14 +08:00 |
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Sebastien Bourdeauducq
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fa83ad0d9c
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drtio: add TX link layer
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2016-09-26 12:53:10 +08:00 |
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Sebastien Bourdeauducq
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2701b914e2
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conda: update migen version requirements
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2016-09-24 21:02:19 +08:00 |