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drtio: always use NoRetiming on MultiReg inputs

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This commit is contained in:
Sebastien Bourdeauducq 2016-10-29 16:37:53 +08:00
parent 9bbc6eb0ef
commit 4f6241283c
2 changed files with 8 additions and 3 deletions
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4
artiq/gateware/drtio/link_layer.py
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@ -3,7 +3,7 @@ from operator import xor, or_
from migen import *
from migen.genlib.fsm import *
from migen.genlib.cdc import MultiReg
from migen.genlib.cdc import MultiReg, NoRetiming
class Scrambler(Module):
@ -248,7 +248,9 @@ class LinkLayer(Module):
rx_remote_rx_ready = Signal()
rx_link_init = Signal()
self.specials += [
NoRetiming(rx.remote_rx_ready),
MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
NoRetiming(rx.link_init),
MultiReg(rx.link_init, rx_link_init, "rtio")
]

7
artiq/gateware/drtio/rt_controller.py
View File

@ -1,5 +1,5 @@
from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.cdc import MultiReg, NoRetiming
from misoc.interconnect.csr import *
@ -44,7 +44,10 @@ class RTController(Module):
self.sync += If(self.kcsrs.counter_update.re,
self.kcsrs.counter.status.eq(self.counter.value_sys))
tsc_correction = Signal(64)
self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
self.specials += [
NoRetiming(self.kcsrs.tsc_correction.storage),
MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
]
self.comb += [
rt_packets.tsc_value.eq(
self.counter.value_rtio + tsc_correction),