srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

drtio: handle underflow/sequence error CSRs

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2016-10-24 20:46:55 +08:00
parent 7dd6eb2f5e
commit c39987b617
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/drtio/rt_controller.py
View File

@ -81,6 +81,14 @@ class RTController(Module):
status_sequence_error = Signal()
self.comb += self.kcsrs.o_status.status.eq(Cat(
status_wait, status_underflow, status_sequence_error))
sequence_error_set = Signal()
underflow_set = Signal()
self.sync += [
If(self.kcsrs.o_underflow_reset.re, status_underflow.eq(0)),
If(self.kcsrs.o_sequence_error_reset, status_sequence_error.eq(0)),
If(underflow_set, status_underflow.eq(1)),
If(sequence_error_set, status_sequence_error.eq(1)),
]
# TODO: collision, replace, busy
cond_sequence_error = self.o_timestamp.storage < last_timestamps.dat_r