forked from M-Labs/artiq
gateware: KC705 satellite target
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import argparse
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from migen import *
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from migen.build.platforms import kc705
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from misoc.cores.i2c import *
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from misoc.cores.sequencer import *
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio import DRTIOSatellite
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# TODO: program Si5324 free-run mode, with automatic switching
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def get_i2c_program(sys_clk_freq):
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# NOTE: the logical parameters DO NOT MAP to physical values written
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# into registers. They have to be mapped; see the datasheet.
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# DSPLLsim reports the logical parameters in the design summary, not
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# the physical register values (but those are present separately).
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N1_HS = 0 # 4
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NC1_LS = 19 # 20
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N2_HS = 1 # 5
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N2_LS = 511 # 512
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N31 = 31 # 32
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i2c_sequence = [
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# PCA9548: select channel 7
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[(0x74 << 1), 1 << 7],
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# Si5324: configure
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[(0x68 << 1), 2, 0b0010 | (4 << 4)], # BWSEL=4
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[(0x68 << 1), 3, 0b0101 | 0x10], # SQ_ICAL=1
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[(0x68 << 1), 6, 0x07], # SFOUT1_REG=b111
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[(0x68 << 1), 25, (N1_HS << 5 ) & 0xff],
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[(0x68 << 1), 31, (NC1_LS >> 16) & 0xff],
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[(0x68 << 1), 32, (NC1_LS >> 8 ) & 0xff],
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[(0x68 << 1), 33, (NC1_LS) & 0xff],
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[(0x68 << 1), 40, (N2_HS << 5 ) & 0xff |
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(N2_LS >> 16) & 0xff],
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[(0x68 << 1), 41, (N2_LS >> 8 ) & 0xff],
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[(0x68 << 1), 42, (N2_LS) & 0xff],
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[(0x68 << 1), 43, (N31 >> 16) & 0xff],
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[(0x68 << 1), 44, (N31 >> 8) & 0xff],
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[(0x68 << 1), 45, (N31) & 0xff],
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[(0x68 << 1), 137, 0x01], # FASTLOCK=1
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[(0x68 << 1), 136, 0x40], # ICAL=1
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]
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program = [
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InstWrite(I2C_CONFIG_ADDR, int(sys_clk_freq/1e3)),
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]
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for subseq in i2c_sequence:
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_START),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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for octet in subseq:
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_WRITE | octet),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_STOP),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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program += [
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InstEnd(),
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]
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return program
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class Si5324ResetClock(Module):
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def __init__(self, platform, sys_clk_freq):
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self.si5324_not_ready = Signal(reset=1)
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# minimum reset pulse 1us
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reset_done = Signal()
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si5324_rst_n = platform.request("si5324").rst_n
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reset_val = int(sys_clk_freq*1.1e-6)
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reset_ctr = Signal(max=reset_val+1, reset=reset_val)
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self.sync += \
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If(reset_ctr != 0,
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reset_ctr.eq(reset_ctr - 1)
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).Else(
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si5324_rst_n.eq(1),
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reset_done.eq(1)
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)
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# 10ms after reset to microprocessor access ready
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ready_val = int(sys_clk_freq*11e-3)
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ready_ctr = Signal(max=ready_val+1, reset=ready_val)
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self.sync += \
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If(reset_done,
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If(ready_ctr != 0,
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ready_ctr.eq(ready_ctr - 1)
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).Else(
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self.si5324_not_ready.eq(0)
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)
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)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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class Satellite(Module):
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def __init__(self, toolchain="vivado"):
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self.platform = platform = kc705.Platform(toolchain=toolchain)
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rtio_channels = []
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for i in range(8):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sma in "user_sma_gpio_p", "user_sma_gpio_n":
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sys_clock_pads = platform.request("clk156")
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self.clock_domains.cd_sys = ClockDomain(reset_less=True)
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self.specials += Instance("IBUFGDS",
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i_I=sys_clock_pads.p, i_IB=sys_clock_pads.n,
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o_O=self.cd_sys.clk)
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sys_clk_freq = 156000000
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i2c_master = I2CMaster(platform.request("i2c"))
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sequencer = ResetInserter()(Sequencer(get_i2c_program(sys_clk_freq)))
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si5324_reset_clock = Si5324ResetClock(platform, sys_clk_freq)
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self.submodules += i2c_master, sequencer, si5324_reset_clock
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self.comb += [
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sequencer.bus.connect(i2c_master.bus),
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sequencer.reset.eq(si5324_reset_clock.si5324_not_ready)
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]
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=sys_clk_freq)
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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self.transceiver.rtio_clk_freq)
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self.submodules.drtio = DRTIOSatellite(
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self.transceiver, self.rx_synchronizer, rtio_channels)
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def build(self, *args, **kwargs):
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self.platform.build(self, *args, **kwargs)
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def main():
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parser = argparse.ArgumentParser(description="KC705 DRTIO satellite")
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parser.add_argument("--toolchain", default="vivado",
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help="FPGA toolchain to use: ise, vivado")
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args = parser.parse_args()
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top = Satellite(args.toolchain)
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top.build()
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if __name__ == "__main__":
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main()
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