forked from M-Labs/artiq
drtio: fixes, add aux packet test
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e59142e344
commit
95d7cba34a
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@ -56,7 +56,7 @@ class LinkLayerTX(Module):
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self.submodules += aux_scrambler
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aux_data_ctl = []
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for i in range(nwords):
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aux_data_ctl.append(self.aux_data[i*2:i*2+1])
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aux_data_ctl.append(self.aux_data[i*2:i*2+2])
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aux_data_ctl.append(0)
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self.comb += [
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If(self.aux_frame,
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@ -129,6 +129,7 @@ class LinkLayerRX(Module):
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self.link_init = Signal()
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self.aux_stb = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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@ -137,7 +138,7 @@ class LinkLayerRX(Module):
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# # #
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aux_descrambler = ResetInserter()(CEInserter()(Scrambler(2*nwords)))
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aux_descrambler = ResetInserter()(CEInserter()(Scrambler(3*nwords)))
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rt_descrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords)))
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self.submodules += aux_descrambler, rt_descrambler
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self.comb += [
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@ -148,9 +149,11 @@ class LinkLayerRX(Module):
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]
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link_init_d = Signal()
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aux_stb_d = Signal()
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rt_frame_d = Signal()
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self.sync += [
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self.link_init.eq(link_init_d),
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self.aux_stb.eq(aux_stb_d),
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self.rt_frame.eq(rt_frame_d)
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]
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@ -160,12 +163,14 @@ class LinkLayerRX(Module):
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link_init_d.eq(1),
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aux_descrambler.reset.eq(1),
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rt_descrambler.reset.eq(1)
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).Else(
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aux_stb_d.eq(1)
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),
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aux_descrambler.ce.eq(1)
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).Else(
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rt_frame_d.eq(1),
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rt_descrambler.ce.eq(1)
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),
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aux_descrambler.i.eq(Cat(*[d.d >> 5 for d in decoders])),
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aux_descrambler.i.eq(Cat(*[d.d[5:] for d in decoders])),
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rt_descrambler.i.eq(Cat(*[d.d for d in decoders]))
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]
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@ -55,7 +55,8 @@ class TestLinkLayer(unittest.TestCase):
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rt_packets = [
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[0x12459970, 0x9938cdef, 0x12340000],
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[0xabcdef00, 0x12345678],
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[0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344]
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[0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344],
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[0x88277475, 0x19883332, 0x19837662, 0x81726668, 0x81876261]
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]
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def transmit_rt_packets():
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while not (yield dut.tx.link_init):
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@ -77,22 +78,77 @@ class TestLinkLayer(unittest.TestCase):
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rx_rt_packets = []
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@passive
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def receive_rt_packets():
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while not (yield dut.rx.link_init):
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yield
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while (yield dut.rx.link_init):
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yield
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previous_frame = 0
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while True:
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frame = yield dut.rx.rt_frame
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if frame and not previous_frame:
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packet = []
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rx_rt_packets.append(packet)
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previous_frame = frame
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if frame:
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packet.append((yield dut.rx.rt_data))
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yield
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aux_packets = [
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[0x12, 0x34],
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[0x44, 0x11, 0x98, 0x78],
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[0xbb, 0xaa, 0xdd, 0xcc, 0x00, 0xff, 0xee]
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]
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def transmit_aux_packets():
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while not (yield dut.tx.link_init):
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yield
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while (yield dut.tx.link_init):
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yield
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for packet in aux_packets:
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yield dut.tx.aux_frame.eq(1)
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for data in packet:
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yield dut.tx.aux_data.eq(data)
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yield
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while not (yield dut.tx.aux_ack):
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yield
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yield dut.tx.aux_frame.eq(0)
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yield
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while not (yield dut.tx.aux_ack):
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yield
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# flush
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for i in range(20):
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yield
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rx_aux_packets = []
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@passive
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def receive_aux_packets():
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while not (yield dut.rx.link_init):
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yield
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while (yield dut.rx.link_init):
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yield
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previous_frame = 0
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while True:
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packet = []
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rx_rt_packets.append(packet)
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while not (yield dut.rx.rt_frame):
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yield
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while (yield dut.rx.rt_frame):
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packet.append((yield dut.rx.rt_data))
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yield
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if (yield dut.rx.aux_stb):
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frame = yield dut.rx.aux_frame
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if frame and not previous_frame:
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packet = []
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rx_aux_packets.append(packet)
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previous_frame = frame
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if frame:
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packet.append((yield dut.rx.aux_data))
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yield
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run_simulation(dut, [link_init(),
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transmit_rt_packets(), receive_rt_packets()])
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transmit_rt_packets(), receive_rt_packets(),
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transmit_aux_packets(), receive_aux_packets()])
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for packet in rx_rt_packets:
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print(" ".join("{:08x}".format(x) for x in packet))
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# print("RT:")
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# for packet in rx_rt_packets:
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# print(" ".join("{:08x}".format(x) for x in packet))
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# print("AUX:")
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# for packet in rx_aux_packets:
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# print(" ".join("{:02x}".format(x) for x in packet))
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self.assertEqual(rt_packets, rx_rt_packets)
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self.assertEqual(aux_packets, rx_aux_packets)
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