forked from M-Labs/artiq
drtio: use additive scrambler reset by link init
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8a92c2c7e5
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e59142e344
@ -5,24 +5,6 @@ from migen import *
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class Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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out = self.i[i] ^ reduce(xor, [curval[tap] for tap in taps])
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self.sync += self.o[i].eq(out)
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curval.insert(0, out)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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class Descrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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@ -33,8 +15,8 @@ class Descrambler(Module):
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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flip = reduce(xor, [curval[tap] for tap in taps])
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self.sync += self.o[i].eq(self.i[i] ^ flip)
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curval.insert(0, self.i[i])
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self.sync += self.o[i].eq(flip ^ self.i[i])
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curval.insert(0, flip)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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@ -70,7 +52,7 @@ class LinkLayerTX(Module):
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# the following meanings:
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# 100 idle/auxiliary framing
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# 0AB 2 bits of auxiliary data
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aux_scrambler = CEInserter()(Scrambler(3*nwords))
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aux_scrambler = ResetInserter()(CEInserter()(Scrambler(3*nwords)))
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self.submodules += aux_scrambler
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aux_data_ctl = []
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for i in range(nwords):
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@ -82,6 +64,7 @@ class LinkLayerTX(Module):
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).Else(
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aux_scrambler.i.eq(Replicate(0b100, nwords))
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),
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aux_scrambler.reset.eq(self.link_init),
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aux_scrambler.ce.eq(~self.rt_frame),
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self.aux_ack.eq(~self.rt_frame)
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]
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@ -98,10 +81,11 @@ class LinkLayerTX(Module):
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# Real-time traffic uses data characters and is framed by the special
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# characters of auxiliary traffic. RT traffic is also scrambled.
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rt_scrambler = CEInserter()(Scrambler(8*nwords))
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rt_scrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords)))
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self.submodules += rt_scrambler
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self.comb += [
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rt_scrambler.i.eq(self.rt_data),
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rt_scrambler.reset.eq(self.link_init),
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rt_scrambler.ce.eq(self.rt_frame)
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]
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rt_frame_r = Signal()
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@ -153,8 +137,8 @@ class LinkLayerRX(Module):
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# # #
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aux_descrambler = CEInserter()(Descrambler(2*nwords))
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rt_descrambler = CEInserter()(Descrambler(8*nwords))
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aux_descrambler = ResetInserter()(CEInserter()(Scrambler(2*nwords)))
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rt_descrambler = ResetInserter()(CEInserter()(Scrambler(8*nwords)))
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self.submodules += aux_descrambler, rt_descrambler
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self.comb += [
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self.aux_frame.eq(~aux_descrambler.o[2]),
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@ -173,7 +157,9 @@ class LinkLayerRX(Module):
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self.comb += [
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If(decoders[0].k,
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If((decoders[0].d == K(28, 7)) | (decoders[0].d == K(29, 7)),
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link_init_d.eq(1)
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link_init_d.eq(1),
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aux_descrambler.reset.eq(1),
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rt_descrambler.reset.eq(1)
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),
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aux_descrambler.ce.eq(1)
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).Else(
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@ -6,7 +6,8 @@ from migen import *
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from artiq.gateware.drtio.link_layer import *
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def process(dut, seq):
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def process(seq):
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dut = Scrambler(8)
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rseq = []
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def pump():
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yield dut.i.eq(seq[0])
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@ -24,17 +25,11 @@ def process(dut, seq):
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class TestScrambler(unittest.TestCase):
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def test_roundtrip(self):
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seq = list(range(256))*3
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq)
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scrambled_seq = process(seq)
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descrambled_seq = process(scrambled_seq)
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self.assertNotEqual(seq, scrambled_seq)
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self.assertEqual(seq, descrambled_seq)
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def test_resync(self):
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seq = list(range(256))
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scrambled_seq = process(Scrambler(8), seq)
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descrambled_seq = process(Descrambler(8), scrambled_seq[20:])
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self.assertEqual(seq[100:], descrambled_seq[80:])
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class Loopback(Module):
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def __init__(self, nwords):
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@ -50,12 +45,24 @@ class TestLinkLayer(unittest.TestCase):
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def test_packets(self):
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dut = Loopback(4)
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def link_init():
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yield dut.tx.link_init.eq(1)
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yield
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yield
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yield dut.tx.link_init.eq(0)
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yield
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rt_packets = [
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[0x12459970, 0x9938cdef, 0x12340000],
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[0xabcdef00, 0x12345678],
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[0xeeeeeeee, 0xffffffff, 0x01020304, 0x11223344]
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]
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def transmit_rt_packets():
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while not (yield dut.tx.link_init):
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yield
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while (yield dut.tx.link_init):
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yield
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for packet in rt_packets:
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yield dut.tx.rt_frame.eq(1)
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for data in packet:
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@ -70,6 +77,11 @@ class TestLinkLayer(unittest.TestCase):
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rx_rt_packets = []
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@passive
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def receive_rt_packets():
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while not (yield dut.tx.link_init):
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yield
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while (yield dut.tx.link_init):
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yield
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while True:
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packet = []
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rx_rt_packets.append(packet)
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@ -78,7 +90,9 @@ class TestLinkLayer(unittest.TestCase):
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while (yield dut.rx.rt_frame):
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packet.append((yield dut.rx.rt_data))
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yield
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run_simulation(dut, [transmit_rt_packets(), receive_rt_packets()])
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run_simulation(dut, [link_init(),
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transmit_rt_packets(), receive_rt_packets()])
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for packet in rx_rt_packets:
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print(" ".join("{:08x}".format(x) for x in packet))
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