forked from M-Labs/artiq
drtio: add RX ready signaling
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@ -2,6 +2,7 @@ from functools import reduce
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from operator import xor, or_
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from migen import *
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from migen.genlib.fsm import *
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class Scrambler(Module):
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@ -33,6 +34,7 @@ class LinkLayerTX(Module):
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.signal_rx_ready = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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@ -43,8 +45,8 @@ class LinkLayerTX(Module):
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# # #
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# Idle and auxiliary traffic use special characters excluding
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# K.28.7 and K.29.7 in order to easily separate the link initialization
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# Idle and auxiliary traffic use special characters excluding K.28.7,
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# K.29.7 and K.30.7 in order to easily separate the link initialization
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# phase (K.28.7 is additionally excluded as we cannot guarantee its
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# non-repetition here).
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# A set of 8 special characters is chosen using a 3-bit control word.
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@ -97,11 +99,14 @@ class LinkLayerTX(Module):
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)
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]
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# During link init, send a series of 1*K.28.7 (comma) + 31*K.29.7
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# During link init, send a series of 1*K.28.7 (comma) + 31*K.29.7/K.30.7
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# The receiving end configures its transceiver to also place the comma
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# on its LSB, achieving fixed (or known) latency and alignment of
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# packet starts.
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# K.29.7 is chosen to avoid comma alignment issues arising from K.28.7.
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# K.29.7 and K.30.7 are chosen to avoid comma alignment issues arising
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# from K.28.7.
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# K.30.7 is sent instead of K.29.7 to signal the alignment of the local
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# receiver, thus the remote can end its link initialization pattern.
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link_init_r = Signal()
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link_init_counter = Signal(max=32//nwords)
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self.sync += [
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@ -109,11 +114,19 @@ class LinkLayerTX(Module):
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If(link_init_r,
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link_init_counter.eq(link_init_counter + 1),
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[k.eq(1) for k in encoder.k],
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[d.eq(K(29, 7)) for d in encoder.d[1:]],
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If(self.signal_rx_ready,
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[d.eq(K(30, 7)) for d in encoder.d[1:]]
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).Else(
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[d.eq(K(29, 7)) for d in encoder.d[1:]]
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),
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If(link_init_counter == 0,
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encoder.d[0].eq(K(28, 7)),
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).Else(
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encoder.d[0].eq(K(29, 7)),
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If(self.signal_rx_ready,
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encoder.d[0].eq(K(30, 7))
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).Else(
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encoder.d[0].eq(K(29, 7))
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)
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)
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).Else(
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link_init_counter.eq(0)
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@ -128,6 +141,7 @@ class LinkLayerRX(Module):
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.remote_rx_ready = Signal()
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self.aux_stb = Signal()
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self.aux_frame = Signal()
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@ -148,19 +162,21 @@ class LinkLayerRX(Module):
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self.rt_data.eq(rt_descrambler.o),
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]
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link_init_d = Signal()
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aux_stb_d = Signal()
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rt_frame_d = Signal()
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self.sync += [
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self.link_init.eq(link_init_d),
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self.aux_stb.eq(aux_stb_d),
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self.rt_frame.eq(rt_frame_d)
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]
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link_init_char = Signal()
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self.comb += [
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link_init_char.eq(
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(decoders[0].d == K(28, 7)) |
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(decoders[0].d == K(29, 7)) |
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(decoders[0].d == K(30, 7))),
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If(decoders[0].k,
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If((decoders[0].d == K(28, 7)) | (decoders[0].d == K(29, 7)),
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link_init_d.eq(1),
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If(link_init_char,
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aux_descrambler.reset.eq(1),
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rt_descrambler.reset.eq(1)
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).Else(
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@ -174,3 +190,19 @@ class LinkLayerRX(Module):
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aux_descrambler.i.eq(Cat(*[d.d[5:] for d in decoders])),
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rt_descrambler.i.eq(Cat(*[d.d for d in decoders]))
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]
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self.sync += [
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self.link_init.eq(0),
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If(decoders[0].k,
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If(link_init_char, self.link_init.eq(1)),
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If(decoders[0].d == K(30, 7),
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self.remote_rx_ready.eq(1)
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).Elif(decoders[0].d != K(28, 7),
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self.remote_rx_ready.eq(0)
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),
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If(decoders[0].d == K(30, 7),
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self.remote_rx_ready.eq(1)
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) if len(decoders) > 1 else None
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).Else(
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self.remote_rx_ready.eq(0)
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)
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]
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