forked from M-Labs/artiq
drtio/rt_packets: fix
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449d1c4dc6
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aa8e211735
@ -509,8 +509,8 @@ class RTPacketMaster(Module):
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rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
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self.submodules += rx_fsm
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echo_reply_now = Signal()
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self.sync.rtio_rx += self.echo_reply_now.eq(echo_reply_now)
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echo_received_now = Signal()
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self.sync.rtio_rx += self.echo_received_now.eq(echo_received_now)
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rx_fsm.act("INPUT",
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If(rx_dp.frame_r,
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@ -518,7 +518,7 @@ class RTPacketMaster(Module):
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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rx_plm.types["error"]: NextState("ERROR"),
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rx_plm.types["echo_reply"]: echo_reply_now.eq(1),
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rx_plm.types["echo_reply"]: echo_received_now.eq(1),
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rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
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"default": [
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error_not.eq(1),
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